A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
2
1
3
4
5
6
7
8
2
1
3
4
5
6
7
8
IC2402
HY5DU561622ETP-D43
256Mbit DDR SDRAM IC
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
39
4
40
41
42
43
44
45
46
47
48
49
5
50
51
52
53
54
55
56
57
58
59
6
60
61
62
63
64
65
66
7
8
9
NR2405
4D02WGJ0150TCE
NR2402
4D02WGJ0150TCE
NR2403
4D02WGJ0150TCE
NR2407
4D02WGJ0150TCE
NR2406
4D02WGJ0150TCE
NR2404
4D02WGJ0150TCE
NR2401
4D02WGJ0150TCE
A13
K17
B13
J16
J17
L15
H17
M15
H16
L16
K16
G17
H15
C13
L17
C14
B17
D16
B14
M16
IC2401 ZR39740HGCF-B0
DTV_ASIC IC
A14
K15
N17
M17
C16
F15
A16
B16
A17
C17
D17
E16
E17
F17
G15
G16
E15
F16
J15
C15
B15
A15
D15
WAS RECEIVED IN GOOD CONDITION AND PICTURE IS NORMAL.
WITH THE DIGITAL TESTER WHEN THE COLOR BROADCAST
NOTE:THE DC VOLTAGE AT EACH PART WAS MEASURED
OF PRINTING AND SUBJECT TO CHANGE WITHOUT NOTICE
NOTE: THIS SCHEMATIC DIAGRAM IS THE LATEST AT THE TIME
R2412
15
R2401
15
R2402
15
R2403
15
R2404
15
R2405
15
R2410
15
R2407
15
R2408
15
R2409
15
R2411
15
R2406
15
R2413
15
R2414
100
R2415
100
R2416
100
C2464
0.1
B
C2462
0.1
B
C2461
0.1
B
C2460
1
B
C2466
1
B
C2463
10 C
C2467
10 C
C2469
1
B
C2468
10 C
C2465
0.1
B
C2459
0.1
B
C2458
0.1
B
C2470
0.1
B
C2471
0.1
B
DDRWEN
SWEN
SDATA3
DDRDQ15
DDRRASN
SRASN
SDATA5
DDRDQ14
DDRBS1
SBS1
SDATA7
DDRDQ13
DDRA0
SADR0
SDATA1
DDRDQ12
DDRA7
SADR7
SDATA0
DDRDQ10
DDRDQ0
DDRDQ15
DDRA5
SADR5
SDATA2
DDRDQ9
DDRA9
SADR9
SDATA6
DDRDQ8
DDRDQ1
DDRDQ14
DDRCKE
SCKE
SDQS0
DDRDQS0
DDRDQ2
DDRDQ13
DDRDQ3
DDRDQ12
DDRA4
SADR4
SDATA9
DDRDQ0
DDRDQ4
DDRDQ11
DDRA12
SADR12
SDATA13
DDRDQ1
DDRDQ5
DDRDQ10
DDRA8
SADR8
SDATA11
DDRDQ2
DDRDQ6
DDRDQ9
DDRA6
SADR6
SDATA12
DDRDQ3
DDRDQ7
DDRDQ8
SDATA10
DDRDQ5
DDRA1
SADR1
SDATA15
DDRDQ6
DDRDQS1
DDRDQS0
DDRA2
SADR2
SDATA8
DDRDQ7
VREF
DDRA3
SADR3
SDQS1
DDRDQS1
DDRA10
SADR10
DDRDQM1
DDRDQM0
DDRA11
SADR11
SDATA4
DDRDQ11
DDRWEN
DDRCKN
DDRCASN
DDRCK
DDRBS0
SBS0
SDATA14
DDRDQ4
DDRRASN
DDRCKE
DDRDQM0
SDQM0
DDRDQM1
SDQM1
DDRA12
DDRBS0
DDRA11
DDRCASN
SCASN
DDRBS1
DDRA9
VREF
DDRA10
DDRA8
DDRCK
SCLK
DDRA0
DDRA7
DDRA1
DDRA6
DDRCKN
SCLKN
DDRA2
DDRA5
DDRA3
DDRA4
DDRCKN
DDRCK
GND
2V6_D
NC
LDQS
UDM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDDQ
NC
NC
VDD
LDM
WE
NC
BA0
BA1
AP/A10
A0
A3
A2
A1
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
NC
UDQS
VREF
VSS
CK
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
NC
A12
VSSQ
CAS
RAS
CS
VSS
1
3
5
7
2
4
6
8
Place cap near pin
DDR Bypass Cap
DDR Bypass Cap
2
4
6
8
1
3
5
7
2
4
6
8
1
3
5
7
SADR0
SADR2
SADR3
SADR4
SADR5
SADR6
SADR7
SADR8
SADR9
SADR10
SADR11
SADR12
SADR13
SBS0
SBS1
SDQM0
SDQM1
SRASN
SCASN
SWEN
SCKE
SCLK
SCLKN
SDQS0
SDQS1
SDATA0
SDATA2
SDATA6
SDATA9
SDATA13
SDATA11
SDATA12
SDATA10
SDATA15
SDATA8
SDATA4
SDATA14
SVREF
SDATA3
SDATA5
SDATA7
SDATA1
Place cap near pin
Place parts near DDR
SADR1
NC
NC
NC
NC
NC
NC
NC
2
1
4
3
5
6
8
7
1
3
5
7
2
4
6
8
2
4
6
8
7
5
3
1
(3/6 DDR)
1
3
5
7
2
4
6
8
Place parts near DDR
FROM AV IN/OUT
PCBDH0
CEF242
(DIGITAL PCB)
AV IN/OUT SCHEMATIC DIAGRAM
H-30
H-29