[V-U388USV]
10/18
A_DDR3_DQU[7]
A_MCLKZ
A_MCLK
A_MCLKE
A_DDR3_BA[1]
A_DDR3_BA[0]
A_WEZ
A_DDR3_DQU[6]
A_DDR3_DQU[5]
A_DDR3_DQU[4]
A_DDR3_DQU[3]
A_DDR3_DQU[2]
A_DDR3_DQU[1]
A_DDR3_DQU[0]
A_DDR3_DQL[7]
A_DDR3_DQL[6]
A_DDR3_DQL[5]
A_DDR3_DQL[4]
A_DDR3_DQL[3]
A_DDR3_DQL[2]
A_DDR3_DQL[1]
A_DDR3_DQL[0]
A_DDR3_DQSL
A_DDR3_DQSU
A_DDR3_A[11]
A_DDR3_A[10]
A_DDR3_A[9]
A_DDR3_A[8]
A_DDR3_A[7]
A_DDR3_A[6]
A_DDR3_A[5]
A_DDR3_A[4]
A_DDR3_A[3]
A_DDR3_A[2]
A_DDR3_A[1]
A_DDR3_A[0]
A_DDR3_DQMU
A_DDR3_DQML
A_RESET
A_RASZ
A_CASZ
[DDR-3 INTERFACE 1/3]
A_DDR3_A[13]
A_DDR3_A[12]
A_DDR3_DQSBU
A_DDR3_DQSBL
A_ODT
A_DDR3_BA[2]
A_DDR3_A[14]
FUNCTION
TITLE
F
D
SH.NO.
DESIGNED BY
8
7
6
5
4
3
2
1
B
PAGE NO.
REV.MARK
DRAWING.NO.
TOSHIBA CORPORATION
A
C
E
5T03655D
F
D
B
A
C
E
127 M_DDRA_DQU7
127
M_DDRA_ADR7
127
M_DDRA_ADR8
127
M_DDRA_ADR3
127
M_DDRA_ADR5
127
M_DDRA_ADR2
127
M_DDRA_ADR10
127
M_DDRA_ADR11
127
M_DDRA_ADR1
127
M_DDRA_ADR4
127
M_DDRA_ADR6
127
M_DDRA_ADR9
127
M_DDRA_ADR12
127
M_DDRA_CLKZ
127
M_DDRA_CLKE
127
M_DDRA_WEZ
127
M_DDRA_BA1
127
M_DDRA_RASZ
127
M_DDRA_CASZ
127
M_DDRA_DQML
127
M_DDRA_BA0
127
M_DDRA_DQMU
127
M_DDRA_CLK
127 M_DDRA_DQSL
127 M_DDRA_DQSU
127
M_DDRA_ADR13
127
M_DDRA_ADR14
127 M_DDRA_DQSBL
127 M_DDRA_DQSBU
127 M_DDRA_ODT
127 M_DDRA_RST
127
M_DDRA_BA2
127 M_DDRA_DQU6
127 M_DDRA_DQU5
127 M_DDRA_DQU4
127 M_DDRA_DQU3
127 M_DDRA_DQU2
127 M_DDRA_DQU1
127 M_DDRA_DQU0
127 M_DDRA_DQL5
127 M_DDRA_DQL3
127 M_DDRA_DQL0
127 M_DDRA_DQL6
127 M_DDRA_DQL2
127 M_DDRA_DQL1
127 M_DDRA_DQL4
127 M_DDRA_DQL7
127
M_DDRA_ADR0
V46A00065300
IC100
MSD388USV-V6
F20
F22
E21
E23
H23
K22
L24
J20
D21
D23
H22
K24
G24
G26
K25
J25
G25
H25
J24
K26
F26
J21
E22
H21
F25
D24
D25
G20
G22
F21
D26
M24
M25
F24
E25
L25
E24
L26
J22
G21
H20
K20
D22
H24
H26
G23
K21
K23
2012.01.19
13:52
OSANAI
MAIN UNIT
MStar (DDR A)
110
11
MP
PE1063ZA
