TKE WCS-10, Руководство пользователя

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WCS-10 User manual 30
Copyright © TK Engineering Oy 2009 - 2017
4.3.8 Filter example for two 32-bit filters using extended ID
The picture below shows the function of one of the two per channel 32-bit filters when using
extended CAN IDs. For a filter to produce a “hit” the ID in
CAN controller register is masked with
the value in the CAN controller acceptance mask register against the value in the CAN controller
acceptance register. A “1” in CAN controller acceptance mask register is masked as don’t care
ID
2
8
ID
2
7
ID
2
6
ID
2
5
ID
2
4
ID
2
3
ID
2
2
ID
2
1
ID
2
0
ID
1
9
ID
1
8
S
R
R
ID
E
ID
1
7
ID
1
6
ID
1
5
ID
1
4
ID
1
3
ID
1
2
ID
11
ID
1
0
ID
9
ID
8
ID
7
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
IDR0 IDR1 IDR2 IDR3
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3
Byte 3 Byte 2 Byte 1 Byte 0
CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3
CAN controller
acceptance mask
register
Byte 3 Byte 2 Byte 1 Byte 0
ID Accepted
ID
2
8
ID
2
7
ID
2
6
ID
2
5
ID
2
4
ID
2
3
ID
2
2
ID
2
1
ID
2
0
ID
1
9
ID
1
8
S
R
R
ID
E
ID
1
7
ID
1
6
ID
1
5
ID
1
4
ID
1
3
ID
1
2
ID
11
ID
1
0
ID
9
ID
8
ID
7
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
IDR0 IDR1 IDR2
A
M
7
A
M
6
A
M
5
A
M
4
A
M
3
A
M
2
A
M
1
A
M
0
CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3
Byte 3 Byte 2 Byte 1 Byte 0
CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3
Byte 3 Byte 2 Byte 1 Byte 0
ID Accepted
CAN controller
acceptance
register
CANopen Byte
CAN controller
ID register
CANopen Byte
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
M
7
A
M
6
A
M
5
A
M
4
A
M
3
A
M
2
A
M
1
A
M
0
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
M
7
A
M
6
A
M
5
A
M
4
A
M
3
A
M
2
A
M
1
A
M
0
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
M
7
A
M
6
A
M
5
A
M
4
A
M
3
A
M
2
A
M
1
A
M
0
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
C
7
A
C
6
A
C
5
A
C
4
A
C
3
A
C
2
A
C
1
A
C
0
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
C
7
A
C
6
A
C
5
A
C
4
A
C
3
A
C
2
A
C
1
A
C
0
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
C
7
A
C
6
A
C
5
A
C
4
A
C
3
A
C
2
A
C
1
A
C
0
ID
6
ID
5
ID
4
ID
3
ID
2
ID
1
ID
0
R
T
R
A
C
7
A
C
6
A
C
5
A
C
4
A
C
3
A
C
2
A
C
1
A
C
0
Figure 5: 32-bit filter using extended ID register
The following picture shows the filter settings for only letting trough extended CAN ID 0x1.
ID
2
8
ID
2
7
ID
2
6
ID
2
5
ID
2
4
ID
2
3
ID
2
2
ID
2
1
ID
2
0
ID
1
9
ID
1
8
S
R
R
ID
E
0
ID
1
6
ID
1
5
ID
1
4
0
ID
1
2
ID
11
ID
1
0
ID
9
ID
8
ID
7
ID
6
ID
5
ID
4
0
ID
2
ID
1
ID
0
R
T
R
IDR0 IDR1 IDR2 IDR3
CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3
Byte 3 Byte 2 Byte 1 Byte 0
CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3
CAN controller
acceptance mask
register
Byte 3 Byte 2 Byte 1 Byte 0
ID Accepted
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
IDR0 IDR1 IDR2
CANIDAR0 CANIDAR1 CANIDAR2 CANIDAR3
Byte 3 Byte 2 Byte 1 Byte 0
CANIDMR0 CANIDMR1 CANIDMR2 CANIDMR3
Byte 3 Byte 2 Byte 1 Byte 0
ID Accepted
CAN controller
acceptance
register
CANopen Byte
CAN controller
ID register
CANopen Byte
ID
2
8
ID
2
7
ID
2
6
ID
2
5
ID
2
4
ID
2
3
ID
2
2
ID
2
1
ID
2
0
ID
1
9
ID
1
8
S
R
R
ID
E
0
ID
1
6
ID
1
5
ID
1
4
0
ID
1
2
ID
11
ID
1
0
ID
9
ID
8
ID
7
ID
6
ID
5
ID
4
0
ID
2
ID
1
ID
0
R
T
R
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
ID
2
8
ID
2
7
ID
2
6
ID
2
5
ID
2
4
ID
2
3
ID
2
2
ID
2
1
ID
2
0
ID
1
9
ID
1
8
S
R
R
ID
E
0
ID
1
6
ID
1
5
ID
1
4
0
ID
1
2
ID
11
ID
1
0
ID
9
ID
8
ID
7
ID
6
ID
5
ID
4
0
ID
2
ID
1
ID
0
R
T
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6: 32-bit filter using extended ID register only accepting extended CAN ID 0x1