THOMSON MK68590 Скачать руководство пользователя страница 5 | Manualshive

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Содержание MK68590

Страница 1: ...iI a M i 1 COMPONENTS COMMUNICATIONS PRODUCTS MOSTEK TECHNICAL MANUAL MK68590 CONTROLLER FOR ETHERNET LOCAL AREA NETWORK 1 91...

Страница 2: ...1 92...

Страница 3: ...er Address Port RAP 2 2 2 3 2 Control and Status Register Definition 2 3 2 3 2 1 Control and Status Register 0 CSRO 2 3 2 3 2 2 Control and Status Register 1 CSR1 2 5 2 3 2 3 Control and Status Regist...

Страница 4: ...ollision Backoff 3 6 3 5 4 Collision Microcode Interaction 3 6 3 5 5 Time Domain Reflectometry 3 6 3 5 6 Heartbeat 3 6 3 6 Reception 3 6 3 6 1 Station Address Detection 3 7 3 6 1 1 Physical Address Re...

Страница 5: ...4 6 LANCE Memory Management 1 6 7 LANCE Pin Assignment 1 7 8 Multiplexed Bus Interface 1 11 9 Demultiplexed Bus Interface 1 12 10 Bus Master Timing 1 13 11 Bus Slave Read Timing for CSRO RAp and CSR3...

Страница 6: ...1 96...

Страница 7: ...ended to operate in a local environment that includes a closely coupled memory and microprocessor The LANCE uses scaled N channel MOS technology and is compatible with several microprocessors A block...

Страница 8: ...3 The variable widths of the packets accommodate both short status command and terminal traffic packets and long data packets to printers and disks 1024 byte disk sectors for ex ample Packets are spa...

Страница 9: ...control registers It is only during this initial phase that the host processor talks directly to LANCE All further communications are handled via a DMA machine under microword control contained withi...

Страница 10: ...UFFER LO ADDRESS STATUS HI ADDRESS BUFFER BYTE LENGTH RECEIVED MESSAGE LENGTH RCV BUFFER LO ADDRESS STATUS HI ADDRESS BUFFER BYTE LENGTH RECEIVED MESSAGE LENGTH XMT BUFFER LO ADDRESS STATUS HI ADDRESS...

Страница 11: ...network cable will be garbled LANCE is constantly monitoring the CLSN Collision pin This signal is generated by the transceiver when the signal level on the network cable indicates the presence of si...

Страница 12: ...paging methods are used within the LANCE and as such the addressing is closest to that used by the MK68000 but is compatible with the others When the LANCE is a bus master a program mable mode of ope...

Страница 13: ...eading the control status register CSRO Bit 06 of CSRO INEA enables or disables interrupts to the microprocessor In a polling mode BIT 07 of CSRO is sampled to determine when an interrupt causing cond...

Страница 14: ...SRO 6 INEA 1 i5A j Data Address Line In Output Tri State Pin 12 DAL IN is an external bus transceiver control line LANCE drives 5A j only while it is the Bus Master When LANCE reads the DAL lines duri...

Страница 15: ...BUSRQ is held low for the entire bus transaction ALE AS Address Latch Enable Output Tri State Pin 18 The active level of Address Strobe is programmable through CSR3 The address portion of a bus trans...

Страница 16: ...ust remain asserted until READY is asserted or READY will not be asserted RESET Bus Reset Signal Input Pin 23 Causes LANCE to cease operation clear its internal logic and enter an idle state with the...

Страница 17: ...IPTION BUS MASTER MODE All data transfers from the LANCE in the Bus Master mode are timed by ALE DAS and READY The automatic adjustment of the LANCE cycle by the READY Signal allows synchronization wi...

Страница 18: ...tches Ap proximately a hundred nanoseconds later DAL 15 00 go into a tristate mode There is a fifty nanosecond delay to allow for transceiver turnaround then BAS falls low to signal the beginning of t...

Страница 19: ...ory device Data is held for 75 nanoseconds after the deassertion of DAS 1 3 7 LANCE INTERFACE DESCRIPTION BUS SLAVE MODE The LANCE enters the Bus Slave Mode whenever CS becomes active This mode must b...

Страница 20: ...stated which configures these lines as inputs The assertion of REAi5Y by LANCE indicates to the memory device that the data on the DAL lines has been stored by LANCE in its appropriate CSR register CS...

Страница 21: ...hernet a Local Area Network Data Link Layer and Physical Layer Specifications Version 2 0 November 1982 2 John F Shoch An Annotated Bibliography on Local Computer Networks October 1979 3 The Ethernet...

Страница 22: ...1 16 1 112...

Страница 23: ...ialization block is comprised of 1 Mode of Operation 1 Word 2 Physical Address 3 Words 3 Logical Address Mask 4 Words 4 Location of Receive and Transmit Descriptor Rings 2 Words 5 Number of Entries in...

Страница 24: ...Bits 15 00 Writing data to the RDP loads data into the CSR selected by RAP Reading the data from RDP reads the data from the CSR selected by RAP CSR1 CSR2 and CSR3 are accessible only when the STOP bi...

Страница 25: ...on Error indicates that the collision input to the chip failed to activate within 2 usec after a chip initiated transmission was completed Collision after transmission is a transceiver test feature CE...

Страница 26: ...rrupt caus ing conditions has occurred BABL MISS MERR RINT TINT IDON If INEA 1 and INTR 1 the INTR output pin will be low INTR is READ ONLY writing this bit has no effect INTR is cleared by RESET or b...

Страница 27: ...ent If STRT and INIT are set together the INIT func tion will be executed first STRT is READIWRITE WITH ONE ONLY Writing a 0 into this bit has no effect STRT is cleared by RESET or by setting the STOP...

Страница 28: ...l not be responded to by LANCE READY will be asserted but no data will be transferred CSR3 is cleared by RESET or by set ting the STOP bit in CSRO 1 1 111 1 0 0 0 0 0 0 0 000 5 4 3 2 1 0 9 8 7 6 5 432...

Страница 29: ...ERTED HIGH ALE ASSERTED LOW is Byte Control Byte Control redefines the Byte Mask and Hold 1 0 Pins BCON is READIWRITE and cleared by RESET or by setting the STOP bit in CSRO BCON o 1 1 0 PIN 16 BiVi1...

Страница 30: ...IADR 23 00 06 IADR 23 00 04 IADR 23 00 02 IADR 23 00 00 The Mode Register allows alteration of LANCE s operating parameters Normal opera tion is with the Mode Register clear IADR 23 00 00 PROM Bit 15...

Страница 31: ...mpts with a retry error reported in TMD3 The number of attempts depends upon the state of DRTY Bit 05 OTCR Bit 03 Disable Transmit CRG When DTCR 0 the transmitter generates and appends a CRC to the tr...

Страница 32: ...tering The first bit of the incoming address must be a 1 for either the Logical Address Filter or the Broadcast Address decode to be enabled Otherwise the in coming address is a physical address and i...

Страница 33: ...of the Logical Ad dress Filter Broadcast Address will also map to bit 47 of the Logical Address Filter If the Logical Address Filter is loaded with all zeroes all incoming logical addresses except Bro...

Страница 34: ...FF C9 28 FF FF FF FF FF 59 29 FF FF FF FF FF 79 30 FF FF FF FF FF 29 15 31 FF FF FF FF FF 19 LAF DESTINATION LOC ADDRESS ACCEPTED DEC HEX 0 32 FF FF FF FF FF D1 33 FF FF FF FF FF F1 34 FF FF FF FF FF...

Страница 35: ...se ad dress lowest address of the Receive Descriptor Ring RDRA Bits 02 00 Must Be Zeros These bits are RDRA 02 00 and must be zeroes because the Receive Rings are aligned on quadword boundaries 2 4 1...

Страница 36: ...to start accessing the descriptor rings and enable it to send and receive packets The LANCE communicates with a HOST device pro bablya microprocessor through the ring structures in memory Each entry i...

Страница 37: ...en it releases the buffer and is cleared by the Host OFLO Bit 12 Overflow Overflow error indicates that the receiver has lost all or part of the incoming packet due to an inability to store the packet...

Страница 38: ...eld is written by the Host and unchanged by LANCE BCNT Bits 11 00 Buffer Byte Count Buffer Byte Count is the length of the buffer pOinted to by this descriptor expressed as a two s complement number T...

Страница 39: ...OWN 1 The host sets the OWN bit after filling the buffer pointed to by the descriptor LANCE clears the OWN bit after transmitting the contents of the buffer Both the Host and LANCE must not alter a d...

Страница 40: ...the Host and is unchanged by LANCE HADR Bits 07 00 The High Order 8 address bits of the buffer pOinted to by this descriptor This field is written by the Host and is unchanged by LANCE 2 5 1 2 3 TRAN...

Страница 41: ...te Collision indicates that a collision has occurred after the slot time of the channel has elapsed lANCE does not retry on late collisions LCOL is set by LANCE and is cleared by the Host lCAR Bit 11...

Страница 42: ...R RINGS IN MEMORY 15 HIGHER ADDRESSES BASE ADDRESS OF TRANSMIT RING TMD 127 TMD 1 TMD O HIGHER ADDRESSES 15 ____________0 2 20 BASE ADDRESS OF RECEIVE RING RMD 127 RMD 1 RMD O 1 132 TRANSMIT RING RECE...

Страница 43: ...s is formed to access the program store which is clocked into the microword register at the end of each cycle 3 2 3 CONTROL DATA PATH The Control Data Path contains the hardware necessary to bUild con...

Страница 44: ...tion between the microprogram and the Bus Master Con trol During block transfer DMA of data memory references overlap LANCE performs up to 8 data transfers before relinquishing HOLD Refer to Chapter 4...

Страница 45: ...fted out Once the SILO has underflowed the SILO locks out further reads and writes until cleared by the microprogram 3 SILO OPERATION RECEPTION Data is loaded into the SILO from the serial input shift...

Страница 46: ...SS MDR 07 00 gets SILO BYTE n MDR 15 08 gets SILO BYTE n 1 MDR 15 08 gets SILO BYTE n MDR 07 00 gets SILO BYTE n 1 RECEPTION BYTE WRITE TO EVEN MEMORY ADDRESS MDR 07 00 gets SILO BYTE n MDR 15 08 don...

Страница 47: ...and CRC transmission is disabled MODE 03 1 and MODE 02 1 4 Mode 03 DTCRC 1 in a normal transmission mode Transmission is indicated at the I O pin by the assertion of TENA with the first bit of the pre...

Страница 48: ...ts the RTRY bit in the current Transmit Message Descriptor 3 in memory and steps over the current transmit buffer 3 5 4 COLLISION MICROCODE INTERACTION The microprogram uses the time provided by COLLI...

Страница 49: ...t bit is a ZERO LANCE will perform a physical address compare The following 47 bits are compared bit for bit for an exact match If they do not match LANCE will reject the packet Bit 00 of the physical...

Страница 50: ...tate of STRT If INIT is clear and STAT is set the microprogram goes on to the Polling routine without going to the Initialization routine If while the STOP bit is set an 1 0 transfer to CSR1 or CSR2 o...

Страница 51: ...es one it stores it in the CDP RAM and waits for byte count overflow or the frame to terminate In this section the receive DMA trap is enabled The descriptor update section is entered when byte count...

Страница 52: ...alization section a buffer lookahead section and a descriptor update section Upon entering the initialization section the first thing the microprogram does is back up the buffer address and byte count...

Страница 53: ...escriptor ring If there was no TX error the byte count is restored and the microprogram returns to the start of the transmit routine to attempt another transmission 3 8 14 DATA CHAIN If Byte Count Equ...

Страница 54: ...1 144...

Страница 55: ...e indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability DC CHARACTERISTICS TA OOC...

Страница 56: ...sing edge of RCLK Note 19 RENA TOPL RENA low time 120 20 RENA TRENH RENA Hold time after rising 40 edge of RCLK 21 CLSN TCPH CLSN high time 80 22 AlDAL TOOFF Bus master driver disable after rising 0 5...

Страница 57: ...ge of 0 DAS Bus slave write 41 ALE TALEW ALE width high 120 150 42 ALE TOALE Delay from rising edge of DAS to the 70 rising edge of ALE 43 DAS Tosw DAS width low 200 44 DAS TAOAS Delay from the 2 J lg...

Страница 58: ...alling edge of ALE 80 to the falling edge of READY to insure a minimum bus cycle time 600 ns 59 READY TSRDS Data setup time to the falling edge of 75 READY Bus slave read 60 READY TRDYH READY hold tim...

Страница 59: ...Figure 15 2 S_ERIAL LINK TIMING DIAGRAM SIA INTERFA CE SIGNALS B O RCLK I _______ _1 8 aff 6 3 RX l JI IJ II XL 7 I M I2 72 7 7 jj 7 15 I lO RENA CLSN t l TCLK TX lENA Timing measurements are made at...

Страница 60: ...WRITE DALO WRITE OALI WAITE READ WRITE CAL 0 15 READ DALO READ DAU READ READ READ BMO 1 NOTE 100 I 200 I 300 I 400 I 500 I 600 I The Bus Master cycle time will increase from a minimum of 600 ns in 100...

Страница 61: ...E BUS SLAVE TIMING DIAGRAM Figure 17 1 55 1 t __ B ____________ rlr 21 5ft ADA wa rTT7 TTT1 TTrm 1 81 62 I READ READI OAlO 15 lREADI 16 I READ WAIT DALQ 5 I WRITE II 59 DATA OUT DATA IN 1 151 J r r I...

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