DTH8040
First issue 12 / 04
MODU_MODE_CTL
FAN_ON
INIT_DONE
NCONFIG
NSTATUS
BUF_OE
PPC_CLK
MEMWAIT
RNOTW
DXX656_BUF
+3V3SD
+5VED
WE1
WE0
SYS_RST
OE
CE2
CE1
GS_IRQ2
DXX_FLD
DXXHSYNC
GS_IRQ1
GS_IRQ0
DXX_RST
EMI_D[0:15]
EMI_AD[1:21]
PCMCLK
KDB_RST
FPA_IRQ
ADMCLK
ODD_ATAPI_RST
ATAPI_DIOR
ATAPI_DIOW
IDE_IRQ
IDE_RST
ATAPI_IORDY
OSSYNC
OSCLK/OSSTB
OS[0:7]
OSREQ
OSVLD
PSTOP
CLAU_RST
CLAHI_INT
CLAHI_CCS
CLAHI_CRE
CLAHI_CWE
CLA_ACLK
NICAM_RST
SV_F/SAPR_HS
SV_R/SAPR_VS
PWR_FAIL
VDEC_FLD
VDEC_HS
VDEC_RST
DGND
PCMLRCLK
PCMSCLK
PCMDATA0
PCMDATA3
DAC_MUTE
27CK_DXX
S_CLK
S_IN
IR
IR_DXX
PWR_DOWN
IR_SAT
SPDIF_OUT
FAN_FAIL
FAN_ON
AV2_PIN8
DGND
AGND
AV_MD[0:15]
AV_MA[0:13]
AV_SDCLK
AV_QDMU
AV_QDML
AV_WE
AV_CAS
AV_RAS
AV_CSO
RASO
CASO
FLASH_WR
CE3
MEMWAIT
PPC_CLK
SYS_CS
E2PROM_EN
I2C_DATA
I2C_CLK
CLA_VID[0:7]
CLA_VCLKI
S_CLK1
S_IN1
1H2H_SEL
I2C_DATA1
B_OUT
G_OUT
Y_OUT
C_OUT
R_OUT
RNOTW
IR_DXX
IR
CE1
DXX_DIOR
DXX_DIOW
+5VED
+1V8SD
+3V3SD
AUD_R_REC
AUD_L_REC
AUD_R_OUT
AUD_L_OUT
VDEC_VS
VDEC_HS
16/9_S2
16/9_S1
SV_R/SAPR_VS
SV_F/SAPR_HS
NICAM_RST
FAN_FAIL
SPDIF_OUT
IR_SAT
EU_CVBS_REC
Y1_REC
TUNER_REC
C1_REC
+5VSA
-5VE
GND
AGND
DGND
CLA_VID[0:7]
CLA_VCLKI
ADSCLK
ADLRCLK
ADSDATA1
CLA_STCLK
27CK_CLA
DGND
EMI_D[0:15]
EMI_AD[1:21]
+3V3SD
+2V5SD
C1_REC
VDEC_VS
VDEC_HS
ADMCLK
DGND
GND
+3V3SD
ADSCLK
ADLRCLK
PCMCLK
PCMLRCLK
PCMSCLK
PCMDATA0
PCMDATA3
DAC_MUTE
DXX_RST
I2C_DATA
I2C_CLK
+12VS_FLASH
DGND
RNOTW
OE
WE1
WE0
EMI_D[0:15]
EMI_AD[1:21]
+3V3SD
I2C_DATA
+3V3SD
I2C_CLK
+3V3SD
+5VSA
27CK_DXX
+12VS_FLASH
PWR_FAIL
ATAPI_DIOR
ATAPI_DIOW
ODD_ATAPI_RST
+2V5SD
+1V8SD
+5VED
+9VE
AGND
PWR_DOWN
+9VE
+5VSA
-5VE
DGND
16/9_S1
16/9_S2
I2C_CLK
I2C_DATA
ADSDATA1
DGND
Y1_REC
EU_CVBS_REC
TUNER_REC
GOB_RST
AUDIO_SEL2
HW_SW
I2C_CLK1
AUDIO_SEL1
AV2_PIN8
RGB_YUV_SEL
RGB_YUV_SEL
Y2_REC/B
C2_REC/R
C2_REC/R
Y2_REC/B
(3) Must be shielded by DGND: 27CK_DXX, CLA_STCLK, 27CK_CLA, ADMCLK, PPC_CLK, S_CLK, S_CLK1, S_IN, S_IN1, I2C_CLK, I2C_CLK1, I2
ENGR: CHEN YC
CIRCUIT DIAGRAM
FROM/TO
FROM
SHT5
SHT7
FROM SHT6
SHT4
FROM SHT2,6
FROM SHT10
FROM/TO
TO SHT4
SHT3
TO SHT8
TO SHT4 & SHT7
BLOCK DIAGRAMS
FROM/TO SHT7
FROM SHT6
TO SHT2
FROM/TO SHT4
SHT2,3,9
TO
SHT5
TO/FROM
FROM SHT7
TO/FR.SHT8
ENGR: CHEN YC
TO SHT8
FROM SHT2
FROM SHT7
FROM/TO SHT7
TO SHT3
TO/FROM SHT6
ENGR: SUN GL
CHEN YC
FROM
SHT8
ENGR: KELVIN
(2) Must be shielded by GND: Y1_REC, CVBS2_REC/G, C1_REC, TUNER_REC, CVBS1_REC, EU_CVBS_REC
Shielding:
(1) Must be shielded by AGND: CV_OOU, Y_OUT, C_OUT, R_OUT, G_OUT, B_OUT, CVBS_DXX, Y_DXX, C_DXX, R_PR2H_DXX, G_Y2H_DXX, B_PB2H_
IDR04_2ND_GEN
FROM SHT4
TO/FROM
SHT8
FROM
SHT7
TO SHT4
FROM /TO
CV_OUT
+3V3SD
+5VED
ADMCLK
ATAPI_IORDY
CLAHI_CCS
CLAHI_CRE
CLAHI_CWE
CLAHI_INT
CLA_ACLK
DGND
DXXHSYNC
DXX_FLD
EMI_AD[1:21]
EMI_D[0:15]
FPA_IRQ
GS_IRQ0
GS_IRQ1
GS_IRQ2
IDE_IRQ
INIT_DONE
KDB_RST
MEMWAIT
NCONFIG
NSTATUS
OSCLK/OSSTB
OSREQ
OSSYNC
OSVLD
OS[0:7]
PCMCLK
PPC_CLK
PSTOP
PWR_FAIL
SV_F/SAPR_HS
SV_R/SAPR_VS
VDEC_FLD
VDEC_HS
ATAPI_DIOR
ATAPI_DIOW
BUF_OE
CE1
CE2
CLAU_RST
DXX656_BUF
DXX_RST
GOB_RST
IDE_RST
NICAM_RST
ODD_ATAPI_RST
OE
RNOTW
SYS_RST
VDEC_RST
WE0
WE1
GOBSTOPPER
SHT4of9
MODU_MODE_CTL
RGB_YUV_SEL
+1V8SD
+3V3SD
+5VED
1H2H_SEL
27CK_DXX
AGND
AUDIO_SEL1
AUDIO_SEL2
AV2_PIN8
AV_MA[0:13]
AV_MD[0:15]
AV_QDML
AV_QDMU
AV_SDCLK
B_OUT
CLA_VCLKI
CLA_VID[0:7]
CV_OUT
C_OUT
DAC_MUTE
DGND
DXXHSYNC
DXX_FLD
EMI_AD[1:21]
EMI_D[0:15]
FAN_FAIL
FAN_ON
FLASH_WR
FPA_IRQ
GS_IRQ0
GS_IRQ1
GS_IRQ2
G_OUT
HW_SW
I2C_CLK
I2C_CLK1
I2C_DATA
I2C_DATA1
INIT_DONE
IR
IR_DXX
IR_SAT
KDB_RST
MEMWAIT
NCONFIG
NSTATUS
PCMCLK
PCMDATA0
PCMDATA3
PCMLRCLK
PCMSCLK
PPC_CLK
PWR_DOWN
R_OUT
SPDIF_OUT
S_CLK
S_CLK1
S_IN
S_IN1
Y_OUT
AV_CAS
AV_CS0
AV_RAS
AV_WE
BUF_OE
CAS0
CE1
CE2
CE3
DXX656_BUF
DXX_DIOR
DXX_DIOW
DXX_RST
E2PROM_EN
GOB_RST
OE
RAS0
RNOTW
SYS_CS
SYS_RST
WE0
WE1
MEMWAIT
PPC_CLK
CE1
IR
IR_DXX
RNOTW
MPEG
DECODER
SHT7of9
+12VS_FLASH
+3V3SD
AV_MA[0:13]
AV_MD[0:15]
AV_QDML
AV_QDMU
AV_SDCLK
DGND
EMI_AD[1:21]
EMI_D[0:15]
FLASH_WR
I2C_CLK
I2C_DATA
MEMWAIT
PPC_CLK
AV_CAS
AV_CS0
AV_RAS
AV_WE
CAS0
CE3
DXX_RST
E2PROM_EN
OE
RAS0
RNOTW
SYS_CS
WE0
WE1
MEMORY
SHT9of9
MODU_MODE_CTL
RGB_YUV_SEL
AV2_PIN8
+5VSA
-5VE
16/9_S1
16/9_S2
1H2H_SEL
AGND
AUDIO_SEL1
AUDIO_SEL2
AUD_L_OUT
AUD_L_REC
AUD_R_OUT
AUD_R_REC
B_OUT
C2_REC/R
Y1_REC
C1_REC
C_OUT
DGND
EU_CVBS_REC
FAN_FAIL
FAN_ON
GND
G_OUT
HW_SW
I2C_CLK1
I2C_DATA1
IR_SAT
R_OUT
SPDIF_OUT
SV_F/SAPR_HS
SV_R/SAPR_VS
S_CLK1
S_IN1
TUNER_REC
VDEC_HS
VDEC_VS
Y2_REC/B
Y_OUT
NICAM_RST
SHT8of9
VOUT
DECODER
MPEG
CV_OUT
+3V3SD
+5VSA
+9VE
-5VE
ADLRCLK
ADSCLK
ADSDATA1
AUD_L_OUT
AUD_L_REC
AUD_R_OUT
AUD_R_REC
DAC_MUTE
DGND
I2C_CLK
I2C_DATA
PCMCLK
PCMDATA0
PCMDATA3
PCMLRCLK
PCMSCLK
AUDIO_CODEC
SHT3of9
TUNER_REC
+3V3SD
16/9_S1
16/9_S2
ADMCLK
C2_REC/R
CLA_VCLKI
CLA_VID[0:7]
C1_REC
Y1_REC
DGND
EU_CVBS_REC
GND
I2C_CLK
I2C_DATA
VDEC_FLD
VDEC_HS
VDEC_VS
VDEC_RST
VDEC_HS
Y2_REC/B
VIDEO_DECODER
SHT2of9
+2V5SD
+3V3SD
27CK_CLA
ADLRCLK
ADSCLK
ADSDATA1
CLAHI_CCS
CLAHI_CRE
CLAHI_CWE
CLAHI_INT
CLA_ACLK
CLA_STCLK
CLA_VCLKI
CLA_VID[0:7]
DGND
EMI_AD[1:21]
EMI_D[0:15]
OSCLK/OSSTB
OSREQ
OSSYNC
OSVLD
OS[0:7]
PSTOP
CLAU_RST
MPEG
ENCODER
SHT5of9
+12VS_FLASH
+1V8SD
+2V5SD
+3V3SD
+5VED
+5VSA
+9VE
27CK_CLA
27CK_DXX
AGND
ATAPI_IORDY
CLA_STCLK
DGND
EMI_AD[1:21]
EMI_D[0:15]
IDE_IRQ
IR
IR_DXX
PWR_DOWN
PWR_FAIL
ATAPI_DIOR
ATAPI_DIOW
CE1
DXX_DIOR
DXX_DIOW
IDE_RST
ODD_ATAPI_RST
RNOTW
CLOCK/ATAPI/PWR
SHT6of9
IDR04 2ND GEN DIGITAL
MPEG
BLOCK DIAGRAMS
(DIGITAL BOARD 1/9)
MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
