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Schematics
range will not be claimed by the bridge. The I/O window for the XIO2001 has a minimum size of 4
KBytes and is naturally 4K-aligned. Typically, most systems use only 16-bit addressing for I/O
transactions, so the upper base and limit registers remain 0.
•
Memory base and memory limit registers – PCI offsets 0×20 and 0×22 : Similar to the I/O base and
limit registers, the bridge must be programmed with a memory address window containing the
nonprefetchable memory resources of all downstream PCI devices requiring nonprefetchable memory.
Memory windows have a minimum size of 1 MByte and are naturally 1M-aligned. The bridge does not
claim either a memory transaction initiated from upstream that does not fall within its memory window
nor memory transactions initiated downstream that do fall within its memory window.
•
Prefetchable memory base, prefetchable memory limit, prefetchable base upper 32-bit, and
prefetchable limit upper 32-bit registers – PCI offsets 0x24, 0x26, 0x28, and 0×2C: Identical to the
memory base and limit registers but for prefetchable memory resources. The prefetchable base upper
32-bit, and prefetchable limit upper 32-bit registers are only used if 64-bit addressing is in use and in
most systems both of these registers will remain all zeroes. If 64-bit addressing is desired and the
memory window for devices behind the XIO2001 resides all or in part in 64-bit memory space then the
prefetchable base upper 32-bit register will combine with the prefetchable base register and the
prefetchable limit upper 32-bit register will combine with the prefetchable limit register to create 64-bit
base and limit registers. All memory addresses between the two addresses will be considered to be
located behind the bridge.
•
For all base and limit registers any case in which the limit register contains a lower address than the
base register will be considered invalid. In this situation the bridge will react as if all resources of that
type resided upstream of the bridge. The bridge will respond to all downstream transactions of that
type with Unsupported Request and will claim and forward upstream any transactions of that type that
initiate on the PCI bus.
Depending on desired functionality, other PCI registers on the XIO2001 may have to be configured.
Consult the XIO2001 Data Manual for a description of the previous registers or for any other XIO2001
registers.
4.4.4
Check Devices Downstream From Bridge
Once the bridge is communicating and is properly configured, check if devices downstream from the
bridge have been configured as required. Check the Windows Device Manager to determine if the device
drivers have been loaded or if other problems exist with the device. Once you have performed these
checks, you can perform PCI transactions on the bus and examine them with any standard PCI analyzer.
5
Schematics
Schematics for the XIO2001 EVM are shown on the following pages.
9
SCPU031A – February 2009 – Revised December 2012
XIO2001 Evaluation Module (EVM)
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