Texas Instruments WiLink WL 1MOD Series, Руководство пользователя

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8.19.6.2 SDIO Switching Characteristics – High Rate
Figure 8-8 and Figure 8-9 show the parameters for maximum clock frequency.
t
THL
t
TLH
V
IH
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
Valid
V
IL
V
IL
V
DD
V
DD
V
SS
V
SS
Not Valid Not Valid
Clock Input
Data Input
t
WL
t
WH
t
ISU
t
IH
50% V
DD
Figure 8-8. SDIO HS Input Timing
t
THL
t
TLH
V
IH
V
IL
V
IH
V
IH
V
OH
Valid
V
OL
V
DD
V
DD
V
SS
V
SS
Not Valid Not Valid
Clock Input
Data Output
t
WL
V
OH
V
OL
t
WH
t
ODLY(max)
t
OH(min)
V
IL
50% V
DD
50% V
DD
Figure 8-9. SDIO HS Output Timing
Table 8-2 lists the SDIO high-rate timing characteristics.
Table 8-2. SDIO HS Timing Characteristics
MIN MAX UNIT
f
clock
Clock frequency, CLK 0.0 52.0 MHz
DC Low, high duty cycle 40.0% 60.0%
t
TLH
Rise time, CLK 3.0 ns
t
THL
Fall time, CLK 3.0 ns
t
ISU
Setup time, input valid before CLK ↑ 3.0 ns
t
IH
Hold time, input valid after CLK ↑ 2.0 ns
t
ODLY
Delay time, CLK ↑ to output valid 7.0 10.0 ns
C
l
Capacitive load on outputs 10.0 pF
WL1801MOD, WL1805MOD, WL1831MOD, WL1835MOD
SWRS152N – JUNE 2013 – REVISED APRIL 2021
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