Software Control
13
SLAU374B – December 2011 – Revised May 2016
Copyright © 2011–2016, Texas Instruments Incorporated
TSW308x Evaluation Module
2.2.4
LMK04800
Figure 8. LMK04800 Tab Control Options
Clock control is determined by register values in the LMK04800 Control tab. The LMK04800 has 12
available output clocks. See the LMK04800 family data sheet for detailed explanations of the register
configurations.
The following LMK04806 outputs are used by the TSW3084EVM:
•
CLK3: DAC3484 DAC sampling clock. This clock type is AC coupled LVPECL. If the DAC3484 is
configured for internal PLL mode, this becomes the reference clock input for the PLL block.
•
CLK8: TSW1400/TSW3100 FPGA input clock. This clock type is AC coupled LVDS. The clock rate
must be set to F
DAC
/interpolation/2.
•
CLK4: DAC3484 FIFO OSTR Clock. This clock type is AC coupled LVPECL.
–
The OSTR signal can be a slower periodic signal or a pulse depending on the application.
–
The OSTR clock rate must be at most F
DAC
/interpolation/8. See the DAC348x data sheet for more
detail.
–
The FIFO OSTR clock must be disabled when the DAC348x is using the on-chip PLL for DACCLK
generation.
•
CLK6: Spare output clock at SMA J5.
•
CLK0: Spare output clock at SMA J2 and J3.
The following LMK04806 outputs are used by the TSW3085EVM:
•
CLK3: DAC3482 DAC sampling clock. This clock type is AC coupled LVPECL. If the DAC3482 is
configured for internal PLL mode, this becomes the reference clock input for the PLL block.
•
CLK8: TSW1400/TSW3100 FPGA input clock. This clock type is AC coupled LVDS. The clock rate
