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Basic Test Procedure with TSW1400

SLAU374B – December 2011 – Revised May 2016

TSW308x Evaluation Module

5. Provide 10-dBm maximum, 300-MHz to 4-GHz LO source to connectors J19 and/or J22. The J19 or

the J22 connector routes the LO source to the respective TRF3705 modulator TX path. Optionally, the
EVM can be configured to share the LO source between the two TX paths through an on-board 3 dB
splitter. The source should be connected to J22 in this case. See the

TX Path Optional Configuration

section for details.

6. Connect the RF output port of J7 and/or J9 to the spectrum analyzer.

7. If an external reference is to be used with LMK04806B in single PLL mode, provide a 3.3-Vpp

maximum, 140-MHz maximum clock to J11. Change SJP5 solder jumper to position 2-3 to route the
external reference source to the LMK04806B OSCIN input.

8. If the LMK04806B is configured in clock distribution mode, provide a 2.4-Vpp maximum, 3.1-GHz

maximum clock to J12. The external clock source will route to the LMK04806B CLKIN1 input.

TSW3084/TSW30H84 EVM Jumpers: (make sure the following jumpers are at their default setting)

Reference Designator

Setting

Function

JP2

1-2

DAC3484/DAC34H84 TXENABLE

JP3

2-3

DAC3484/DAC34H84 SLEEP

JP4

1-2

10-MHz TCXO Enable

JP12, JP13

2-3

TRF3705 Power Down

JP14, JP15

2-3

TRF3705 Gain Control

SJP2

2-3

CPLD EEPROM W/P

SJP3

1-2

USB Bus Power

SJP4

1-2

CPLD Clock Select

SJP5

1-2

Internal/External Reference Select for LMK04806B OSCIN

SJP9, SJP10, SJP11, SJP12

2-3

DAC3484/DAC34H84 DATACLK delay. Default is zero trace
delay.

TSW3085 EVM

1. Connect J13 connector of TSW3085 EVM to J4 connector of TSW1400 EVM.

2. Connect the EVM-supplied 18-AWG wires to the DC plug cable (Tensility 10-01776) to a qualified lab

bench power supply. The 18-AWG red wire is the 6-V wire while the 18-AWG black wire is the ground
wire.

3. Connect the 6-V power supply cable to the J4,

Power In

jack of the TSW3085 EVM.

4. Connect PC’s USB port to J14 USB port of the TSW3085 EVM. The cable should be a standard A to

mini-B connector cable.

5. Provide 10 dBm maximum, 300-MHz to 4-GHz LO source to connectors J1. The J1 connector routes

the LO source to the respective TRF3705 modulator TX path.

6. Connect the RF output port of J7 to the spectrum analyzer.

7. If an external reference is to be used with LMK04806B in single PLL mode, provide a 3.3-Vpp

maximum, 140 MHz maximum clock to J11. Change SJP5 solder jumper to position 2-3 to route the
external reference source to the LMK04806B OSCIN input.

8. If the LMK04806B is configured in clock distribution mode, provide a 2.4-Vpp maximum, 3.1-GHz

maximum clock to J12. The external clock source will route to the LMK04806B CLKIN1 input.

Содержание TSW308 Series

Страница 1: ... 1 1 Overview 3 1 2 EVM Block Diagram 4 2 Software Control 7 2 1 Installation Instructions 7 2 2 Software Operation 7 3 Basic Test Procedure with TSW1400 17 3 1 TSW1400 Overview 17 3 2 Test Block Diagram for TSW1400 17 3 3 Test Setup Connection 18 3 4 TSW308x Example Setup Procedure 20 4 Basic Test Procedure with TSW3100 24 4 1 TSW3100 Overview 24 4 2 Test Block Diagram for TSW3100 25 4 3 Test Set...

Страница 2: ...rogram 21 16 Load DAC Firmware Prompt 21 17 Load File to Transfer into TSW1400 22 18 TSW308x WCDMA Output TRF3705 Low Gain Mode 23 19 TSW308x WCDMA Output TRF3705 High Gain Mode 23 20 TSW3100 FPGA Clock 100 Ω LVDS Termination at Pins T31 and T32 of the FPGA 24 21 TSW3100 and TSW3084 TSW30H84 Test Setup Block Diagram 25 22 TSW3100 and TSW3085 Test Setup Block Diagram 26 23 TSW3100 GUI for LVDS DDR ...

Страница 3: ...om 300 MHz to 4 GHz to up convert the I Q outputs from the DAC to RF The default RF signal paths is the direct TRF3705 I Q modulator output To add flexibility to the RF evaluation the modulator outputs can also connect to the optional RF amplifier and programmable attenuator path to meet additional test conditions and requirements The EVM can be used along with TSW1400 or TSW3100 to perform a wide...

Страница 4: ... CLK8p CLK8n OSCIN CLKIN1 REF Out CLKOUTP CLKOUTP CLKOUTN CLK4p CLK4n CLK3p CLK3n LVDS DC Coupled DATA 16 DATACLK FRAME SYNC PARITY Ext CLK Input 2 4 Vpp MaxSingle Ended 3 1GHz Max AC coupled FPGA CLK 1 TSW1400 TSW3100 LVDS AC coupled REF In Introduction www ti com 4 SLAU374B December 2011 Revised May 2016 Submit Documentation Feedback Copyright 2011 2016 Texas Instruments Incorporated TSW308x Eva...

Страница 5: ...p CLK0n CLK6p CLK8p CLK8n OSCIN CLKIN1 REF In REF Out CLKOUTP CLKOUTP CLKOUTN CLK4p CLK4n CLK3p CLK3n DATA 16 DATACLK FRAME SYNC PARITY Reference LVCMOS Level Reference for LMK04806B PLL Mode Ext CLK Input 2 4 Vpp MaxSingle Ended 3 1GHz Max AC coupled FPGA CLK 1 TSW1400 TSW3100 LVDS AC coupled www ti com Introduction 5 SLAU374B December 2011 Revised May 2016 Submit Documentation Feedback Copyright...

Страница 6: ...GA CLK 2 TSW1400 LVDS AC coupled J11 J16 J5 J2 J3 MUX 3dB Splitter RF RF LO LO Q Q I I J7 J9 J1 9 J22 RF1 RF2 LO 1 LO2 Default Path Optional Path J13 High Speed Samtec Connector CLK0p CLK0n CLK6p CLK8p CLK8n CLK9p CLK9n OSCIN CLKIN 1 REF In REF Out CLKOUTP CLKOUTP CLKOUTN CLK4p CLK4n CLK3p CLK3n LVDS DC Coupled DATA 32 DATACLK FRAME SYNC PARITY Introduction www ti com 6 SLAU374B December 2011 Revi...

Страница 7: ...ram Files x86 Texas Instruments TSW308x 5 When plugging in the USB cable for the first time you are prompted to install the USB drivers a When a pop up screen opens select Continue Downloading b Follow the onscreen instructions to install the USB drivers c If needed the drivers can be accessed directly in the install directory 2 2 Software Operation The software allows programming control of the D...

Страница 8: ...plement or offset binary Parity provides configuration of the parity input PLL Settings provides configuration of the on chip PLL circuitry Temperature Sensor provides temperature monitoring of DAC348x die temperature 2 2 1 1 FIFO Settings The DAC348x has 8 samples deep FIFO to relax the timing requirement of a typical transmitter system The FIFO has an input pointer and an output pointer and both...

Страница 9: ...l on chip PLL clock then the OSTR signal is the internally generated PFD frequency See the Dual Sync Sources Mode in the relevant DAC348x data sheet for details 2 2 1 2 LVDS Delay Settings Depending on the signal source implementation that is TSW1400 TSW3100 or FGPA system the following options can be implemented to meet the minimum setup and hold time of DAC348x data latching Set the on chip LVDS...

Страница 10: ...nd 3 3 GHz 6 Set VCO Bias Tune to 1 7 Charge Pump setting a If stability P M is less than 120 then set to Single b If stability P M is greater than 120 then set to Double or install external loop filter 8 Adjust the Freq Tune Coarse accordingly For additional information see the relevant DAC348x data sheet 2 2 2 Digital Tab Control Options Figure 6 Digital Tab Control Options DAC348x Interpolation...

Страница 11: ... last OSTR sync from the external LVPECL OSTR signal Clock divider sync must be enabled with OSTR set as sync source SYNC sync from the external LVDS SYNC signal SIF SYNC sync from SIF Sync Uncheck and check the SIF Sync button for sync event QMC Adjustment allows adjustment of the gain and phase of the I Q channel to minimize sideband power of the modulator output REGWR auto sync from SIF registe...

Страница 12: ... reference output polarity and output delay Data Routing provides flexible routing of the A B C and D digital path to the desired output channels Note The DAC3482 does not support this mode DAC Gain configures the full scale DAC current and DAC3484 DAC3482 mode With Rbiasj resistor set at 1 28 kΩ DAC Gain 15 for 30 mA full scale current DAC Gain 10 for 20 mA full scale current default Output Shuto...

Страница 13: ... CLK8 TSW1400 TSW3100 FPGA input clock This clock type is AC coupled LVDS The clock rate must be set to FDAC interpolation 2 CLK4 DAC3484 FIFO OSTR Clock This clock type is AC coupled LVPECL The OSTR signal can be a slower periodic signal or a pulse depending on the application The OSTR clock rate must be at most FDAC interpolation 8 See the DAC348x data sheet for more detail The FIFO OSTR clock m...

Страница 14: ...ration CLK6 Spare output clock at SMA J5 CLK0 Spare output clock at SMA J2 and J3 The clock settings are divided into subcontrol sections These sections allow the user to set the divide ratio digital delay type analog delay and ON OFF control Note that clock pairs share several settings The OSCout control section allows the user to configure the settings for the OSCIN input The TSW308xEVM uses thi...

Страница 15: ...ftware Control 15 SLAU374B December 2011 Revised May 2016 Submit Documentation Feedback Copyright 2011 2016 Texas Instruments Incorporated TSW308x Evaluation Module Figure 9 LMK04800 Advanced Settings Control Panel ...

Страница 16: ...le Click on Send All to ensure all the values are loaded properly Save Regs saves the register configuration for all devices 2 2 6 Attenuator Control Figure 10 RF Attenuator Control Each of the RF path on the TSW308xEVM contains a 50 Ω RF digitally controlled attenuator that operates from DC to 4 GHz This highly versatile digital step attenuator DSA covers a 0 dB to 31 75 dB attenuation range in 0...

Страница 17: ...d TSW308x Evaluation Module 3 Basic Test Procedure with TSW1400 This section outlines the basic test procedure for testing the EVM with the TSW1400 3 1 TSW1400 Overview The TSW1400 is a high speed data capture and pattern generator board When functioning as a pattern generator it has a maximum LVDS bus rate of 1 5 GSPS and this allows evaluation of the DAC348x and also DAC34SH84 with maximum 750 M...

Страница 18: ...or 1 Connect the EVM supplied 18 AWG wires to the DC plug cable Tensility 10 01776 to a qualified lab bench power supply The 18 AWG red wire is the 5 V wire while the 18 AWG black wire is the ground wire 2 Connect a 5 V power supply cable to J12 the 5V_IN jack of the TSW1400 EVM 3 Connect PC s USB port to J5 USB port of the TSW1400 EVM The cable should be a standard A to mini B connector cable TSW...

Страница 19: ... 3 DAC3484 DAC34H84 SLEEP JP4 1 2 10 MHz TCXO Enable JP12 JP13 2 3 TRF3705 Power Down JP14 JP15 2 3 TRF3705 Gain Control SJP2 2 3 CPLD EEPROM W P SJP3 1 2 USB Bus Power SJP4 1 2 CPLD Clock Select SJP5 1 2 Internal External Reference Select for LMK04806B OSCIN SJP9 SJP10 SJP11 SJP12 2 3 DAC3484 DAC34H84 DATACLK delay Default is zero trace delay TSW3085 EVM 1 Connect J13 connector of TSW3085 EVM to ...

Страница 20: ...on folder and load example files The example files are located at C Program Files Texas Instruments TSW308x Configuration Files To configure the LMK04806B in single PLL mode select the file in the LMK04806 PLL Mode 10 MHz reference folder To configure the LMK04806B in clock distribution mode select the file in the LMK04806 Clock Distribution Mode folder For the TSW3084 the files contain settings f...

Страница 21: ...Start the High Speed Converter Pro GUI program When the program starts select the DAC tab and then select appropriate device in the Select DAC menu Figure 15 Select DAC348x Family in the High Speed Converter Pro GUI Program 2 When prompted Do you want to update the firmware for DAC select YES Figure 16 Load DAC Firmware Prompt 3 Click on the button labeled Load File to transfer into TSW1400 locate...

Страница 22: ...F30MHz_Fdata614 4MHz_1000 tsw under C Program Files Texas Instruments High Speed Data Converter Pro 1400 Details Testfiles 6 Enter 307 2M or 614 4M for the Data Rate and 2 s complement for the DAC Option 7 Select Hanning for Window 8 In the DAC Selection panel on the left side of the GUI click on Send to load the data into memory 9 Toggle the SIF SYNC button of the TSW308x EVM GUI to synchronize t...

Страница 23: ...1 2016 Texas Instruments Incorporated TSW308x Evaluation Module NOTE Baseband 30 MHz NCO 30 MHz with NCO Gain disabled QMC Gain 1446 LO 1780 MHz Figure 18 TSW308x WCDMA Output TRF3705 Low Gain Mode NOTE Baseband 30 MHz NCO 30 MHz with NCO Gain disabled QMC Gain 1446 LO 1780 MHz Figure 19 TSW308x WCDMA Output TRF3705 High Gain Mode ...

Страница 24: ...document assumes that the TSW3100 software is installed and functioning properly The TSW308x needs TSW3100 operating software version 2 5 or higher with TSW3100 board Rev D or higher The TSW308xEVM sends the FPGA reference clock to the FPGA of the TSW3100EVM in LVDS format Therefore a 100 Ω LVDS termination resistor is needed at the TSW3100 FPGA clock input All the latest TSW3100EVMs from TI have ...

Страница 25: ...ath configurations such as x 3dB splitter for LO source x Additional RF amp and attenuator path See Optional Configuration Section for detail RF J9 LO J22 RF J7 LO J19 TX_AB TX_CD Cross over Ethernet Cable www ti com Basic Test Procedure with TSW3100 25 SLAU374B December 2011 Revised May 2016 Submit Documentation Feedback Copyright 2011 2016 Texas Instruments Incorporated TSW308x Evaluation Module...

Страница 26: ... the TSW3100 pattern generation board is shown in Figure 22 Figure 22 TSW3100 and TSW3085 Test Setup Block Diagram 4 3 Test Setup Connection TSW3100 Pattern Generator 1 Connect the EVM supplied 18 AWG wires to the DC plug cable Tensility 10 01776 to a qualified lab bench power supply The 18 AWG red wire is the 5 V wire while the 18 AWG black wire is the ground wire 2 Connect 5 V power supply cable...

Страница 27: ... output See Figure 23 for details Change Interpolation value to DAC Clock Rate Interpolation 3 84 that is 1228 8 2 3 84 160 Enter desired Offset Frequency that is 30 MHz for each desired carrier Select the LVDS output button Check the LOAD and Run box Press the green Create button Figure 23 TSW3100 GUI for LVDS DDR Format For TSW3084 configure the TSW3100 to output a 307 2 MSPS LVDS Quad Interleav...

Страница 28: ...propriate digital blocks if example file with NCO setting is used 3 Verify the spectrum using the Spectrum Analyzer at the two RF outputs of the TSW308xEVM J7 for TSW3085 J7 and J9 for TSW3084 and TSW30H84 4 With 1780 MHz of LO the expect results are shown in Figure 18 TRF3705 Low Gain Mode and Figure 19 TRF3705 High Gain Mode 5 Optional Configuration The onboard LMK048000 has the following config...

Страница 29: ...wing steps must be made to the EVM Replace oscillator Y1 with a VCXO such as a FVXO HC73 series 3 3 V VCXO from Fox Install R273 R274 R90 C177 and C300 Provide an external reference at SMA J12 Select the Dual PLL options in the LMK04800 Control tab Consult the LMK04800 data sheet for proper device configuration for this mode of operation 6 Transmit Path Optional Configuration 6 1 Shared LO Path TS...

Страница 30: ... A d j a c e nt C h a n n e l B a n d w i dt h 3 8 4 M H z L o w e r 7 3 9 1 d B S p a c i n g 5 M H z U p p e r 7 4 0 5 d B A l t e r n at e C h a n n e l B a n d w i dt h 3 8 4 M H z L o w e r 7 8 2 0 d B S p a c i n g 1 0 M H z U p p e r 7 8 6 7 d B P O S 4 2 7 8 dB m Transmit Path Optional Configuration www ti com 30 SLAU374B December 2011 Revised May 2016 Submit Documentation Feedback Copyrig...

Страница 31: ...igh Speed Data Capture Pattern Generator Card SLWU079 TSW3100 High Speed Digital Pattern Generator SLUU101 FMC DAC ADAPTER Physical Design Database Rev D Board SLOR102 TSW3084EVM Design Package SLAC515 TSW30H84EVM Design Package SLAC517 TSW308x EVM Software SLAC507 High Speed Data Converter Pro software SLWC107 Revision History NOTE Page numbers for previous revisions may differ from page numbers ...

Страница 32: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Страница 33: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Страница 34: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Страница 35: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Страница 36: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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