Texas Instruments TSW14J58 JESD204C Скачать руководство пользователя страница 9 | Manualshive

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Texas Instruments TSW14J58 JESD204C Скачать руководство пользователя страница 9

Note

SYNCA, SYNCB, and SYNCC SMAs are used to provide external SYNC signals from the FPGA. The
cables of each SYNC signal should have equal length to ensure the signal arrives at the same time for
all boards using these SYNCs. The TRIG IN SMA connector can be used to trigger the FPGA from an
external source. All four SMAs use 3V3 logic CMOS signals. The EVM has onboard translators to set
these inputs/outputs to the correct voltage levels for the FPGA.

3.3.3.2 FPGA Mezzanine Card (FMC+) Connector

The TSW14J58 EVM has one connector to allow for the direct plug in of TI JESD204C_B serial interface
ADC and DAC EVMs. The specifications for this connector are mostly derived from the ANSI/VITA 57.4 FPGA
Mezzanine Card (FMC+) Standard. This standard describes the compliance requirements for a low-overhead
protocol bridge between the IO of a mezzanine card and an FPGA processing device on a carrier card. This
specification is being used by FPGA vendors on their development platforms.

The FMC+ connector, J3, provides the interface between the TSW14J58EVM and the ADC or DAC EVM under
test. This 560-pin Samtec high-speed, high-density connector (part number ASP-184329-01) is suitable for
high-speed differential pairs up to 32.5 Gbps.

In addition to the JESD204B/C standard signals, several CMOS single-ended signals and LVDS differential
signals are connected between the FMC+ and FPGA. In the future, these signals may allow the HSDC Pro GUI
to control the SPI serial programming of ADC and DAC EVMs that support this feature. The connector pinout
description is shown in

Table 3-5. FMC+ Connector Description of the TSW14J58

FMC+ Signal Name

FMC+ Pin

Standard JESD204 Application

Mapping

Description

RXP/N0_0

C6 and C7

Lane 0± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N1_0

A2 and A3

Lane 1± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N2_0

A6 and A7

Lane 2± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N3_0

A10 and A11

Lane 3± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N0_1

A14 and A15

Lane 4± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N1_1

A18 and A19

Lane 5± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N2_1

B16 and B17

Lane 6± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N3_1

B12 and B13

Lane 7± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N0_2

B8 and B9

Lane 8± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N1_2

B4 and B5

Lane 9± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N2_2

Y10 and Y11

Lane 10± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N3_2

Z12 and Z13

Lane 11± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N0_3

Y14 and Y15

Lane 12± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N1_3

Z16 and Z17

Lane 13± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N2_3

Y18 and Y19

Lane 14± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

RXP/N3_3

Y22 and Y23

Lane 15± (M → C)

JESD Serial data transmitted from mezzanine and received by carrier

TXP/N0_0

C2 and C3

Lane 0± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N1_0

A22 and A23

Lane 1± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N2_0

A26 and A27

Lane 2± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N3_0

A30 and A31

Lane 3± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N0_1

A34 and A35

Lane 4± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N1_1

A38 and A39

Lane 5± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N2_1

B36 and B37

Lane 6± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N3_1

B32 and B33

Lane 7± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N0_2

B28 and B29

Lane 8± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N1_2

B24 and B25

Lane 9± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N2_2

Z24 and Z25

Lane 10± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N3_2

Y26 and Y27

Lane 11± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

TXP/N0_3

Z28 and Z29

Lane 12± (C → M)

JESD Serial data transmitted from carrier and received by mezzanine

Hardware Configuration

SLWU094 – MARCH 2021

Submit Document Feedback

TSW14J58 JESD204C Data Capture and

Pattern Generator Card

9

Copyright © 2021 Texas Instruments Incorporated

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Содержание TSW14J58 JESD204C

Страница 1: ...Memory Device 11 Figure 3 2 Programming Memory Device 12 Figure 3 3 Config file 13 Figure 4 1 TSW14J58EVM Serial Number 15 Figure 4 2 High Speed Data Converter Pro GUI Top Level 15 Figure 4 3 Hardware Device Manager 16 Figure 5 1 Select ADC Firmware to be Loaded 17 Figure 5 2 Download Firmware Error Message 17 List of Tables Table 3 1 Switch Description of the TSW14J58 Device 6 Table 3 2 Jumper De...

Страница 2: ...te data sheet performance specifications Using the Xilinx JESD204C IP core the TSW14J58 can be dynamically configurable to support lane speeds from 1 Gbps to 24 5 Gbps from 1 to 16 lanes Together with the accompanying High Speed Data Converter Pro Graphic User Interface GUI it is a complete system that captures and evaluates data samples from ADC EVMs generates and sends desired test patterns to D...

Страница 3: ...58 The FPGA stores the data received into the board DDR4 memory module The data from memory is then read by the FPGA and transmitted to a DAC EVM across the FMC interface connector The board contains a 200 MHz oscillator used to generate the DDR4 reference clock and a general purpose clock shows the TI TSW14J58 evaluation module Figure 2 1 TSW14J58EVM The major features of the TSW14J58 are Backwar...

Страница 4: ...th support for USB and JTAG reconfigurable JESD core parameters L M K F HD S and more ILA configuration data accessible through USB and JTAG Dynamically reconfigurable Transceiver data rate Serial lane operating range from 1 to 24 5 Gbps Figure 2 2 shows a block diagram of the TSW14J58 EVM Power Regulators USB 2 0 Port EEPROM EEPROM JTAG Connector USB to Parallel USB 3 0 Port 24 Gb DDR4 RAM Xilinx...

Страница 5: ... information such as number of lanes number of converters octets per frame and other parameters This information is loaded into the FPGA registers after the user clicks on the capture button After the parameters are loaded synchronization is established between the data converter and FPGA and valid data is then captured into the onboard memory See the High Speed Data Capture Pro GUI Software User ...

Страница 6: ...e 3 1 Table 3 1 Switch Description of the TSW14J58 Device Component Description SW1 USB 2 0 reset SW2 USB 3 0 reset SW3 FPGA hardware reset SW4 Force FPGA firmware load from selected EEPROM SW5 Board main power switch 3 2 2 Jumpers The TSW14J58 contains several jumpers JP and solder jumpers SJP that enable certain functions on the board The description of the jumpers is found in Table 3 2 Table 3 ...

Страница 7: ... With shunt on pins 2 3 U47 is enabled 1 to 2 J34 Status LEDs enable With shunt on pins 1 2 LEDs are disabled With shunt on pins 2 3 LEDs are enabled 1 to 2 J35 EPROM select With shunt on pins 2 3 select is controlled by USB2 0 With shunt on pins 1 2 U3 is selected With shunt removed U6 is selected 2 to 3 www ti com Hardware Configuration SLWU094 MARCH 2021 Submit Document Feedback TSW14J58 JESD20...

Страница 8: ...he shunt on J34 to pin 2 3 3 3 3 Connectors 3 3 3 1 SMA Connectors The TSW14J58 has 5 SMA connectors Table 3 4 defines the connectors Table 3 4 SMA Connectors Component Connector Description J12 REFCLKP1 Spare external FPGA reference clock Must install C527 and remove C552 to use this input This connects to FPGA clock input ball H7 J13 REFCLKN1 Spare external FPGA reference clock Must install C528...

Страница 9: ...P N2_1 B16 and B17 Lane 6 M C JESD Serial data transmitted from mezzanine and received by carrier RXP N3_1 B12 and B13 Lane 7 M C JESD Serial data transmitted from mezzanine and received by carrier RXP N0_2 B8 and B9 Lane 8 M C JESD Serial data transmitted from mezzanine and received by carrier RXP N1_2 B4 and B5 Lane 9 M C JESD Serial data transmitted from mezzanine and received by carrier RXP N2...

Страница 10: ...GPIO_DIFF_P N 9 F19 and F20 Alt DAC SYNC M C Alternate carrier bound SYNC signal for use in class 0 1 2 JESD204B systems GPIO_DIFF_P N 9 H31 and H32 Alt SYNC C M Alternate ADC mezzanine bound SYNC signal For use when SYNC C M is not available Special Purpose I O GPIO_C6 F1 Spare from FPGA pin G25 GPIO_C3 K10 Spare from FPGA pin U24 GPIO_C5 K14 Spare from FPGA pin AF13 GPIO_C10 K7 Spare from FPGA p...

Страница 11: ...r J35 determines which EEPROM will configure the FPGA when switch SW4 is pressed After power up pressing SW4 will load the FPGA with the factory pre programmed flash device U3 if J35 has a shunt between pins 1 2 and U6 if the shunt is between pins 2 3 or removed Program the Memory Device To program U3 and U6 with new files use the following steps Note Install Vivado version 2018 3 or later Lab Edi...

Страница 12: ...am Configuration Memory Device see Figure 3 2 Figure 3 2 Programming Memory Device Hardware Configuration www ti com 12 TSW14J58 JESD204C Data Capture and Pattern Generator Card SLWU094 MARCH 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Страница 13: ...is provides the interface between the HSDC Pro GUI running on a PC using the Microsoft Windows operating system and the FPGA For the computer the drivers needed to access the USB port are included on the HSDC Pro GUI installation software that can be downloaded from the web The drivers are automatically installed during the installation process On the TSW14J58EVM the USB port is used to identify t...

Страница 14: ...ace modes become available that are not currently supported by the latest release of HSDC Pro GUI the HSDCProv_xpxx_Patch_setup executable available on the TI website under the High Speed Data Converter Pro Software product folder http www ti com tool DATACONVERTERPRO SW will allow the user to add these to the GUI device list After the patch has been downloaded follow the on screen instructions to...

Страница 15: ...connections and that power switch SW5 is in the on position Remove the USB3 0 cable from the board then re install Click on the Instrument Option tab at the top left of the GUI and selecting Connect to the Board If this still does not correct this issue check the status of the host USB port www ti com Software Start Up SLWU094 MARCH 2021 Submit Document Feedback TSW14J58 JESD204C Data Capture and ...

Страница 16: ...manager The USB 2 0 device will be listed as USB Serial Converter A B C and D If the drivers are present in the device manager window and the software still does not connect remove the USB cables from the board then reconnect them Attempt to connect to the board using the GUI If the problem still exists cycle power to the board and repeat the prior steps Figure 4 3 Hardware Device Manager Software...

Страница 17: ...e Type in the lower right corner and LEDs D16 D17 DDR Calib and PLL lock should all turn white Figure 5 1 Select ADC Firmware to be Loaded For information regarding the use of the TSW14J58EVM with a TI ADC or DAC JESD204C_B serial interface EVM consult the High Speed Data Converter Pro GUI User s Guide and the individual EVM User s Guide available on www ti com If the message appears as shown in F...

Страница 18: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Страница 19: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Страница 20: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Страница 21: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Страница 22: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Страница 23: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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