Texas Instruments TSW14J58 JESD204C, Руководство пользователя, Страница: 10 / 23

Table 3-5. FMC+ Connector Description of the TSW14J58 (continued)
FMC+ Signal Name FMC+ Pin Standard JESD204 Application
Mapping
Description
TXP/N1_3 Y30 and Y31 Lane 13± (C → M) JESD Serial data transmitted from carrier and received by mezzanine
TXP/N2_3 Z8 and Z9 Lane 14± (C → M) JESD Serial data transmitted from carrier and received by mezzanine
TXP/N3_3 Y6 and Y7 Lane 15± (C → M) JESD Serial data transmitted from carrier and received by mezzanine
J3_REFCLKP/N0_0 D4 and D5 DEVCLKA± (M → C) Primary carrier-bound reference clock required for FPGA giga-bit transceivers.
Equivalent to device clock.
J3_REFCLKP/N1_0 B20 and B21 Alt. DEVCLKA± (M → C) Alternate Primary Carrier-bound reference clock required for FPGA giga-bit
transceivers. For use when DEVCLKA (M → C) is not available
J3_REFCLKP/N1_1 Z20 and Z21 Alt. (M → C) Alternate Primary Carrier-bound reference clock required for FPGA giga-bit
transceivers. For use when DEVCLKA (M → C) is not available
Device Clock, SYSREF, and SYNC
GPIO_DIFF_P/N<9> G6 and G7 DEVCLKB± (M → C) Secondary carrier-bound device clock. Used for special FPGA functions such
as sampling SYSREF
GPIO_DIFF_P/N<3> G9 and G10 SYSREF± (M → C) Carrier-bound SYSREF signal
GPIO_DIFF_P/N<2> G12 and G13 SYNC± (C → M) ADC mezzanine-bound SYNC signal for use in class 0/1/2 JESD204 systems
AC14_P/N F10 and F11 DAC SYNC± (M → C) Carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems
GPIO_DIFF_P/N<9> F19 and F20 Alt. DAC SYNC± (M → C) Alternate carrier-bound SYNC signal for use in class 0/1/2 JESD204B systems
GPIO_DIFF_P/N<9> H31 and H32 Alt. SYNC± (C → M) Alternate ADC mezzanine-bound SYNC signal. For use when SYNC (C → M)
is not available
Special Purpose I/O
GPIO_C6 F1 Spare from FPGA pin G25
GPIO_C3 K10 Spare from FPGA pin U24
GPIO_C5 K14 Spare from FPGA pin AF13
GPIO_C10 K7 Spare from FPGA pin AF15
GPIO_B25 K13 Spare from FPGA pin AE13
GPIO_B26 K11 Spare from FPGA pin Y23
GPIO_D15 K8 Spare from FPGA pin Y16
ACLK D11 Spare from FPGA pin W12
ASDIO D12 Spare from FPGA pin W13
PRESENT H2 Present USB2.0 input. Indicates if a mezzanine card is present
ASDO D26 Spare from FPGA pin G11
ASEN D27 Spare from FPGA pin G9
PRESENT_Z1 Z1 Present USB2.0 input. Indicates if a mezzanine card is present.
K4_P/K4_N K4 and K5 REFCLKP1_3 to FPGA pin H7 and H6
CSB_ADC D17 Spare from FPGA pin AA13
CSB_LMK D18 Spare from FPGA pin AF13
CSB_LMX D20 Spare from FPGA pin AF14
SCLK C22 Spare from FPGA pin W12
SDI C23 Spare from FPGA pin W13
SDO_ADC C26 Spare from FPGA pin Y13
SDO_LMK C27 Spare from FPGA pin AE13
SCL C30 Spare USB2.0 I/F
SDA C31 Spare USB2.0 I/F
NCOA0 J18 Spare from FPGA pin AF15
NCOA1 J19 Spare from FPGA pin Y16
NCOB0 J21 Spare from FPGA pin G22
NCOB1 J22 Spare from FPGA pin F22
CDBUS2-5 G27, G28, G33,
G34 Spare USB2.0 I/O's
DDBUS0-3 G21, G22, G36,
G37 Spare USB2.0 I/O's
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10 TSW14J58 JESD204C Data Capture and
Pattern Generator Card SLWU094 – MARCH 2021
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