V
= 2 V / div
OUT
Time = 2 msec / div
EN = 2 V / div
V = 10 V / div
IN
V
= 2 V / div
OUT
Time = 2 msec / div
EN = 2 V / div
V = 10 V / div
IN
Test Setup and Results
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SLVUB76 – July 2017
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TPS54335AEVM-010 3-A Regulator Evaluation Module
2.9
Powering Up
Figure 11
and
Figure 12
show the start-up waveforms for the TPS54335AEVM-010. In
Figure 11
, the
output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1and
R2 resistor divider network. In
Figure 12
, the input voltage is initially applied and the output is inhibited by
using a jumper at JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN
voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps
up to the externally set value of 5 V. The input voltage for these plots is 24 V and the load is 5
Ω
.
Figure 11. TPS54335AEVM-010 Start-Up Relative to V
IN
Figure 12. TPS54335AEVM-010 Start-up Relative to Enable
