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4.4
Memory Cell Reference Voltage Load (LOAD1)
4.5
Termination Voltage Load (LOAD2)
4.6
Fan
4.7
Power Up/Power Down Procedure
5
EVM Assembly Drawing and Layout
EVM Assembly Drawing and Layout
LOAD1 is an electronic or resistive load sinking less than 10 mA from the VTTREF pin voltage of 1.25 V
(DDRI Mode) or 0.9 V (DDRII Mode). LOAD1 should be connected between pins Vtt_Ref and
Vtt_Ref_GND
LOAD2 is an electronic load set in constant current mode capable of sinking 0 A to 3 A of current at 1.25
V (DDRI Mode) or 0.9 V (DDRII Mode). LOAD2 needs to be connected between pins VTT OUT and GND
OUT. LOAD2 and V
VTT OUT
should never be on at the same time.
Most power converters include components that can get hot to the touch when operating, approaching
temperatures of 60
°
C. Because this EVM is not enclosed to allow probing of circuit nodes, a small fan
capable of 200-400 LFM is recommended to reduce component temperatures when operating the
evaluation module.
The following test procedure is recommended primarily for power up and shutting down the EVM.
Whenever the EVM is running, the fan should be turned on. Also, never walk away from a powered EVM
for extended periods of time.
1. Working at an ESD workstation, make sure that any wrist straps, boot straps or mats are connected
referencing the user to earth ground before power is applied to the EVM. Electrostatic smock and
safety glasses should also be worn.
2. Connect power supplies, loads, voltage meters and current meters as shown in Figure 1.
3. Set 100mil shunt jumper as described in User Configuration Jumper Settings for desired operational
configuration. (Note: Do not attempt to change jumper settings during operation)
4. Increase V
VDDQ
from 0 V to 1.8 or 2.4V DC. Using V4, verify V
VDDQ
voltage between 1.5 and 3.4V.
5. Increase V
V5IN
from 0 V to 5.0 VDC. Using V1, verify V
V5IN
voltage between 4.75 V and 5.25 V.
6. Vary V
VTT OUT
for A3 from 0 A to -2 A. (Note: Do not run both V
VTT OUT
and LOAD2 at the same time)
7. Set V
VTT OUT
to 0 V and disconnect.
8. Vary LOAD2 for A3 from 0 A to 2 A. (Note: Do not run both V
VTT OUT
and LOAD2 at the same time)
9. Vary LOAD1 from 0 mA to 10 mA. (Note: Do not exceed 10 mA on LOAD1)
10. Vary V
VDDQ IN
from 1.5 V to 3.4 V
11. Vary V
V5IN
from 4.75 V to 5.25 V
12. Use state S3 and state S5 switches to test sleep states.
13. Decrease LOAD1 to 0 mA.
14. Decrease LOAD2 to 0 A.
15. Decrease V
V5IN
to 0 V.
16. Decrease V
VDDQ IN
to 0 V.
TPS51100 is built on a double sided copper clad FR4 PCB 3.0”
×
3.0” and 0.062 thick. Figure 4 through
Figure 7 detail the PCB assembly, silk screen and copper layers for TPS51100EVM. These figures are
provided for reference and evaluation purposes only.
Using the TPS51100
6
SLUU201–JULY 2004
