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Description
4
SLVUAP7A – April 2016 – Revised September 2016
Copyright © 2016, Texas Instruments Incorporated
TPS25740EVM-741 and TPS25740AEVM-741 Evaluation Module User
Guide
2
Description
Referring to the schematic in
and
, a 12-V DC input is applied at the J1/J3 terminals or
J4 connector. The voltage at the DCDC_OUT node is regulated by the LM5175PWP buck-boost regulator
(U1) and associated circuitry. This provides a nominal 5-V, 5-A output for the TPS25740/TPS25740A (U2)
and associated output load.
A type C upstream facing port (UFP) is plugged in at J9. When TPS25740/TPS25740A detects the UFP
via CC1 or CC2 then it will activate Q6/Q10 with the GDNG signal. This will apply the default VBUS
voltage of 5 V at J9 to the UFP. A USB PD capable device can now request the power delivery
capabilities from the TPS25740/TPS25740A which are programmed by J7 and J8. Once the UFP knows
the voltage capabilities of the DFP then it can now request a different VBUS voltage.
The voltage change request gets processed by the TPS25740/TPS25740A and is relayed to the LM5175
regulator through the CTL1 and CTL2 pins. R21 and R24 program the default 5-V output at DCDC_OUT.
R22 and R19 are switched in by CTL1 and CTL2 respectively and are placed in parallel with R24 to
change the feedback voltage regulation point. Capacitors C31 and C32 provide slew rate control in order
to comply with the USB PD specification.
For more information and detailed design information, refer to the TPS25740/TPS25740A datasheet,
(
).