www.ti.com
EVM Assembly Drawing and Layout Guidelines
13
SLVUAG7A – May 2015 – Revised July 2017
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
TPS2378EVM-602 Evaluation Module
7.2
Layout Guidelines
The layout of the PoE front end should follow power and EMI/ESD best-practice guidelines. A basic set of
recommendations include:
•
Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer,
diode bridges, TVS and 0.1-
μ
F capacitor, and TPS2378 converter input bulk capacitor.
•
Make all leads as short as possible with wide power traces and paired signal and return.
•
No crossovers of signals from one part of the flow to another are allowed.
•
Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input
voltage rails and between the input and an isolated converter output.
•
Place the TPS2378 over split, local ground planes referenced to VSS for the PoE input and to
COM/RTN for the converter. Whereas the PoE side may operate without a ground plane, the converter
side must have one. Do not place logic ground and power layers under the Ethernet input or the
converter primary side.
•
Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay
copper fills in the power path.
The DC/DC Converter layout benefits from basic rules such as:
•
Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay
copper fills in the power path.
•
Minimize trace length of high current, power semiconductors, and magnetic components.
•
Where possible, use vertical pairing
•
Use the ground plane for the switching currents carefully.
•
Keep the high-current and high-voltage switching away from low-level sensing circuits including those
outside the power supply.
•
Proper spacing around the high-voltage sections of the converter
