Texas Instruments TPS23525EVM-815, Руководство пользователя

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General Configuration and Description
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4 SLVUB36 – October 2017
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TPS23525EVM-815 Evaluation Module
3 General Configuration and Description
3.1 Physical Access
Table 2 lists the TPS23525EVM connector and functionality, Table 3 describes the test point availability,
and Table 4 describes the default jumper configuration.
Table 2. Connector Functionality
Connector Label Description
J1, J2, J3 RTN Power bus input - Tie the high-side of power-supply inputs and outputs here
J7 Neg48V_B Power bus input - Tie the low-side of power-supply B input here
J8 Vout_FLTD Output bus - Apply the low-side load here (if applicable)
J9 CAUX Connect to auxiliary bulk capacitor (if applicable)
J10 Neg48V_A Power bus input - Tie the low-side of power-supply A input here
Table 3. Test Points
Connector Label Description
TP1 RTN High-side power-supply input and high-side output load voltage
TP2 VCC Clamped voltage supply
TP3 PGB Power Good Bar
TP4 SS Soft-start pin voltage
TP5 UVEN UV pin voltage
TP6 D D pin voltage
TP7 OV OV pin voltage
TP8 GATE Gate drive output voltage for hot-swap FET
TP9 SNS Sense pin test point
TP10 TMR Timer capacitor voltage
TP11 GATEB Gate drive output voltage for Gate B ORing FET
TP12 GATEA Gate drive output voltage for Gate A ORing FET
TP13, TP15 VEE IC ground - Place voltage probe ground at this pin
TP14 Neg48VB Low-side input for power-supply B
TP16 HS_DRAIN Drain voltage of the hot-swap FET
TP17 VOUT_FLTD Low-side output for load
TP18 Neg48VA Low-side input for power-supply A
TP19 - Open-drain output for power good signal. Attach to downstream EN pin.
Table 4. Jumper Descriptions
Connector Description
J5 Jump pins 1-2 to enable UV (default), or jump pins 2-3 to tie UV to VCC (disable)
J6 Leave open to enable OV (default), or jump pins 1-2 to tie OV to GND (disable)