Q2
5V-PU
GND
GND
Orange
D2
OTW_CLIP
5V-PU
GND
GND
MONITORS
100
R33
100
R35
FAULT
GND
GND
GND
GND
GND
GND
GND
GND
GND
PVDD
GND
GND
PVDD
GND
GND
GND
GND
RESET
GND
GND
GVDD
0.1uF
C22
GND
IN1_P
IN1_M
5V-PU
SLAVE MODE
MASTER MODE (600 kHz)
MASTER MODE AM1 (533 kHz)
MASTER MODE AM2 (480 kHz)
GND
FREQUENCY
ADJUST
OUT2_M
IN2_M
IN2_P
1.00k
R29
1.00k
R31
100pF
C64
100
R23
100pF
C58
100
R19
100pF
C30
100
R10
100pF
C19
100
R5
OUT1_P
OUT1_M
OUT1+
OUT1-
OUT2+
OUT2-
1
2
3
4
5
6
7
8
J16
1µF
C56
3.30
R54
GND
GND
GND
GND
1µF
C53
1µF
C51
1µF
C50
TP2
OUT1_P
TP5
OUT1_M
TP9
OUT2_M
TP4
PVDD
TP8
PVDD
TP3
OUT1+
TP10
OUT1-
TP11
OUT2+
TP12
OUT2-
J13
FAULT
0
R30
VDD
GVDD
FAULT
OTW_CLIP
GND
OSCILLATOR
SYNC
INTERFACE
4
1
2
3
J17
1µF
C41
TP26
FREQ_ADJ
TP21
IN1M
TP22
IN2P
TP23
IN2M
TP19
AVDD
TP15
GVDD
TP16
VDD
1000pF
100V
C25
1000pF
100V
C36
1000pF
100V
C44
1000pF
100V
C60
10µH
L6
TP20
IN1P
OUT1+
OUT1-
OUT2-
OUT2+
IN1P
IN1M
IN2P
IN2M
FROM ANALOG
OTW_CLIP
TO
ANALOG
FRONT END
GND
GND
6
4
5
1
3
S1
RESET
GND
0.1uF
C67
GND
0.1uF
C18
4.02k
R26
GND
PVDD
100k
R6
GND
GND
1
GND
2
MR
5
RESET
3
VDD
4
U7
TPS3802K33DCKR
GND
RESET CONTROL
RESET-SW
RESET
RESET-SW
Q1
TO AIB
OTW_CLIP
FAULT
CONTROLLER
RESET-SW
1µF
100V
C32
1µF
100V
C33
1µF
100V
C47
1µF
100V
C48
1µF
100V
C42
1µF
100V
C34
Red
D4
FAULT
0.033µF
C27
0.033µF
C29
OUT2_P
TP7
OUT2_P
0.033µF
C52
0.033µF
C54
TP6
GND
GND
OSCM
OSCP
OSCM
OSCP
FREQ_ADJ
FREQ_ADJ
TP1
OTW_CLIP
TP14
FAULT
5V-PU
J6
HEAD
GND
TP18
HEAD
10.0k
R68
49.9k
R15
30.0k
R17
47.0k
R24
47.0k
R28
HEAD
CMUTE
IN1_P
IN1_M
IN2_P
IN2_M
GAIN/SLV
VDD
AVDD
100k
R76
GAIN/SLV MATRIX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J23
Gain/SLV Select
47.0k
R72
100k
R77
5.60k
R41
GND
GND
GND
GND
GND
GND
GND
16.0k
R36
GND
MSTR-18dB
MSTR-24dB
MSTR-30dB
MSTR-34dB
SLV-18dB
SLV-24dB
SLV-30dB
SLV-34dB
100k
R42
100k
R61
75.0k
R73
51.0k
R74
39.0k
R34
47.0k
R27
51.0k
R21
AVDD
GND
6
4
5
1
3
S2
CMUTE
GND
5V-PU
PVDD
GVDD
3.32
R75
1µF
C66
Using 10uH and 1uF, Cut-off is 50kHz
10µH
L2
10µH
L3
10µH
L4
10µH
L5
1µF
C24
1µF
C35
1µF
C43
1µF
C59
NT2
Net-Tie
AUGNDR
AUGNDR
AUGNDR
AUGNDL
AUGNDL
NT1
Net-Tie
AUGNDL
OUT1_P
OUT1_M
OUT2_P
OUT2_M
TP24
GAIN/SLV
1.00k
R38
0.033µF
C16
GND
47.0k
R1
5V-PU
5V-PU
5V-PU
FRONT END
1.00k
R32
3.30
R55
3.30
R56
3.30
R53
V-EXT
1
2
3
J22
VDD SEL
0
R37
GVDD
TP34
5V-EXT
TP33
5V-PU
5V
0
R3
1000µF
C31
1000µF
C46
TP35
CMUTE
J24
J9
J2
TP13
RESET
VDD-SEL
GVDD
20.0k
R69
39.0k
R71
75.0k
R78
VDD
1
CMUTE
17
IN1_P
8
IN1_M
9
FREQ_ADJ
14
OSCM
12
OSCP
13
GND
5
GND
6
AVDD
21
HEAD
11
IN2_P
15
IN2_M
16
RESET
10
FAULT
4
GAIN/SLV
2
OTW_CLIP
3
GVDD
22
BST1_P
44
BST1_M
43
BST2_M
23
BST2_P
24
GND
42
GND
41
GND
25
GND
26
GND
34
GND
33
OUT1_P
40
OUT1_P
39
OUT1_M
35
OUT2_P
32
OUT2_M
27
OUT2_M
28
PVDD
38
PVDD
37
PVDD
36
PVDD
31
PVDD
30
PVDD
29
GND
18
GND
19
GND
20
GND
7
GND
45
TPA3220DDWR
U4
10.0k
R79
10.0k
R80
GND
5V-PU
Copyright © 2017, Texas Instruments Incorporated
EVM Design Documents
20
SLAU754A – January 2018 – Revised August 2019
Copyright © 2018–2019, Texas Instruments Incorporated
TPA3220 Evaluation Module
Figure 13. TPA3220 EVM Schematic 2