Hardware Configuration
12
SLAU754A – January 2018 – Revised August 2019
Copyright © 2018–2019, Texas Instruments Incorporated
TPA3220 Evaluation Module
3.6
EVM Power Tree
The TPA3220EVM includes a few options for power configuration so that various input types can be
evaluated.
3.6.1
TPA3220 Supplies
The TPA3220 device has a few power supplies which each have their own voltage range and rules.
Details for each supply are as shown:
•
PVDD
– This is the main device supply which accepts from 7 V to 30 V. Power output of the device is
derived solely from PVDD and therefore it is important to configure this supply according to the chosen
output configuration and load. Complete details are included in
.
•
VDD
– This supply is used for the non-PVDD power of the device for blocks such as the front-end and
control circuitry. The TPA3220 internal 5-V LDO is also powered by this pin. VDD can be powered by 5
V directly if using the TPA3220 with the internal regulator OFF. In this case, tie the GVDD and AVDD
pins directly to VDD using
J22
position 2:3. When the internal regulator is used, VDD must be between
7 V and PVDD through J22 position 1:2 or providing an external voltage to V-EXT. GVDD and AVDD
are only 5-V tolerant so
J22
cannot be in position 2:3. The 5 V TP or 5 V through J24 must be used to
power GVDD and AVDD separate from VDD in this case.
•
GVDD
and
AVDD
– These pins are used for the gate drive and analog supply of the device. These
pins accept only 5 V. When the internal regulator is used, these pins are fed internal to the device, no
external connection is necessary. When the internal regulator is OFF, these pins need 5 V through the
TP or 5 V through J24 as previously mentioned.
Table 7. Power Supply Summary
PVDD (V)
VDD (V)
AVDD and GVDD
Internal Regulator
Status
Note
7.0 to 30.0
5.0
Externally Provided
OFF
Most Efficient
7.0 to 30.0
7.0 to PVDD
No Connection to VDD
ON
5 V internally generated
X
5.0 to 7.0
-
-
Not allowed (do not use)
3.6.2
TPA3220EVM Power Options
All options in this section assume the TPA3220 internal 5-V regulator is OFF and that 5 V is provided
externally to VDD, AVDD, and GVDD. J22 must be in position 2:3 to connect VDD to the AVDD and
GVDD nodes. The major input configurations are listed in the following sections by the supplies available.
3.6.2.1
PVDD Only (12 V to 30 V)
This power mode is the default setup when the board is tested and shipped. The user can connect any
valid supply voltage to J1 and the onboard LDOs will generate the required non-PVDD voltages. PVDD
itself always connects directly to the TPA3220 PVDD pins. Setup for this mode is the same as described
in
3.6.2.2
PVDD (12 V to 30 V) and One Non-5-V Supply
This power mode is useful for certain applications where a system has one higher voltage used for PVDD
and a second lower voltage that may be used for device pullups and other supplies (VDD, GVDD, and
AVDD). The PVDD voltage can still be connected to J1 but jumpers J29 and J24 as well as resistor R37
must be removed.
The non-5-V supply should be connected to jumper V-EXT (7 V to 30 V only) and J25 in position 2:3 to
select V-EXT as the input for U5. Install J19 to enable U5. Install R16 to connect 5VPU-VR to 5V-PU and
J22 in position 2:3 to connect 5V-PU to VDD.
