Peripheral Architecture
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2.7
Reset Considerations
2.7.1
Software Reset Considerations
Two bits in the power and emulation management register (PWREMU_MGMT) control resetting the parts
of the UART:
•
The UTRST bit controls resetting the transmitter only. If UTRST = 1, the transmitter is active;
if UTRST = 0, the transmitter is in reset.
•
The URRST bit controls resetting the receiver only. If URRST = 1, the receiver is active;
if URRST = 0, the receiver is in reset.
In each case, putting the receiver and/or transmitter in reset will reset the state machine of the affected
portion but does not affect the UART registers.
2.7.2
Hardware Reset Considerations
When the processor RESET pin is asserted, the entire processor is reset and is held in the reset state
until the RESET pin is released. As part of a device reset, the UART state machine is reset and the UART
registers are forced to their default states. The default states of the registers are shown in
Section 3
.
2.8
Initialization
The following steps are required to initialize the UART:
1. Perform the necessary device pin multiplexing setup (see the device-specific data manual).
2. Program the VDD3P3V_PWDN register to power up the IO pins for the UART (see the device-specific
data manual).
3. Set the desired baud rate by writing the appropriate clock divisor values to the divisor latch registers
(DLL and DLH).
4. If the FIFOs will be used, select the desired trigger level and enable the FIFOs by writing the
appropriate values to the FIFO control register (FCR). The FIFOEN bit in FCR must be set first, before
the other bits in FCR are configured.
5. Choose the desired protocol settings by writing the appropriate values to the line control register
(LCR).
6. If autoflow control is desired, write appropriate values to the modem control register (MCR). Note that
all UARTs do not support autoflow control, see the device-specific data manual for supported features.
7. Choose the desired response to emulation suspend events by configuring the FREE bit and enable the
UART by setting the UTRST and URRST bits in the power and emulation management register
(PWREMU_MGMT).
2.9
Interrupt Support
2.9.1
Interrupt Events and Requests
The UART generates the interrupt requests described in
Table 5
. All requests are multiplexed through an
arbiter to a single UART interrupt request to the CPU, as shown in
Figure 8
. Each of the interrupt requests
has an enable bit in the interrupt enable register (IER) and is recorded in the interrupt identification
register (IIR).
If an interrupt occurs and the corresponding enable bit is set to 1, the interrupt request is recorded in IIR
and is forwarded to the CPU. If an interrupt occurs and the corresponding enable bit is cleared to 0, the
interrupt request is blocked. The interrupt request is neither recorded in IIR nor forwarded to the CPU.
2.9.2
Interrupt Multiplexing
The UARTs have dedicated interrupt signals to the DSP CPU and the interrupts are not multiplexed with
any other interrupt source.
18
Universal Asynchronous Receiver/Transmitter (UART)
SPRU997C – December 2009
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