C55_l2EnableMIR1
2-36
C Interface
Syntax
C55_l2EnableMIR1(mir1mask);
Parameters
LgUns
mir1mask;/* disable mask */
Return Value
Void
Description
This API applies to the OMAP 2320 platform only.
C55_l2EnableMIR1 enables level 2 interrupts by clearing the bits
specified by mir1mask in the Interrupt Mask Register1 (MIR1). The MIR1
is a register in the Level 2 Interrupt Controller (L2IC) that defines which
level 2 interrupts (32-63) are enabled or disabled. (Cleared bits are
enabled.)
This function provides the functionality of C55_enableIer0/1 for level 2
interrupts. The mir1mask argument is a 32-bit bitmask that defines which
level 2 interrupts to enable.
Example
// Enables L2 interrupts 42, 43, 44, 45
// 0x3c00 = 11110000000000 binary
C55_l2EnableMIR1(0x00003c00);
See Also
C55_l2EnableMIR1
Enable certain level 2 interrupts