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TLC32040 AIC Initialization
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4.3 TLC32040 AIC Initialization
To use the TLC32040 analog interface circuit (AIC), you must follow a se-
quence of steps to initialize and set up the ’C31’s timer and serial port, and to
reset and program the AIC. The following subsections describe this process.
Resetting the AIC
As shown in Figure 4–1, page 4-3, the ’C31’s XF0 signal is connected to the
RESET signal of the AIC. By toggling the RESET signal, the ’C31 can reset
the AIC. This is achieved by executing the following instructions:
rpts 40 ; Execute next instruction 40x
ldi 2h,IOF ; Pull AIC into reset
ldi 6h,IOF ; Pull AIC out of reset
Initializing the ’C31 timer
As shown in Figure 4–1, page 4-3, the ’C31’s timer (TCLKO) signal is con-
nected to the AIC’s master clock (MCLK) signal. The MCLK signal drives all
the key logic signals of the AIC, such as the shift clock, the switched-capacitor
filter clocks, and the A/D and D/A timing signals. The timer pulses the TCLK0
signal whenever the ’C31 timer counter register (memory mapped to
0x0080 8024h) counts up to the timer period register (memory mapped to
0x0080 8028h) value. Then, the timer counter registers reset to zero and re-
peat. (For a detailed description of the ’C31 timer, refer to the
TMS320C3x
User’s Guide). Because of differences between the maximum frequency of the
’C31’s timer and the maximum and minimum frequencies of the AIC, the fol-
lowing constraints should be observed:
-
Minimum Timer Period Register Value.The ’C31 50 MHz can generate
a maximum timer frequency of 12.5 MHz (CLKIN/4), which is above the
AIC’s tested master clock frequency maximum of 10 MHz. If you use fre-
quencies beyond those listed in the TLC32040 data sheet the resulting
performance may not be predictable. If the timer is run in pulse mode (con-
trol value is 0x2C1) the minimum period of 1 results in 12.5-MHz master
pulse rate and 2 results in 6.25 MHz. See the
TLC32040 Data Sheet
(SLAS014) for more information.