Texas Instruments TMS320C3 Series, Руководство пользователя, Страница: 153 / 166

Host Interface Control Design Notes
B-13 DSK Circuit Board Dimensions and Schematic Diagrams
NC CLK STRB A23 A22 A21 A20 NC DEMO T1 T0 RW TRI GND
NC HPIS USERR HPIA UBOOT INT2 READY NC SRAM USERX USERW Q1 Q0 VCC
global
;– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
EQUATIONS ;
READY.TRST = TRI ;
INT2.TRST = TRI ;
INT2 = HPIS ;
HPIA = /(A23 * A22 * A21 * /STRB) + /TRI ; 245 enable and HPIA
Q0 := INT2 ; 1st tap
Q1 := Q0 ; 2nd tap for pulse gen
READY = /(Q0*/Q1) * (A23*A22*A21*A20*/STRB)
;
;
; A23 A22 A21 A20 /STRB
;
SRAM = /( A23*/A22 */STRB)
USERR = /( A23* A22*/A21 */STRB* RW)
USERW = /( A23* A22*/A21 */STRB* /RW)
USERX =(/DEMO* /( A23* A22*/A21 */STRB)) +(DEMO* ((T0*/T1)+(/T0*T1)))
UBOOT =(/DEMO* /(/A23*/A22*/A21*/A20*/STRB)) +(DEMO*/((T0*/T1)+(/T0*T1)))
;– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
; The decoded address ranges are as follows
; NOTE: By using A23 as an enable, it is possible to use external
; zero wait state RAM. Essentialy by ignoring decoded outputs
;– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
; USER_BOOT 000000 0FFFFF EPROM boot or uP mode operation
; 100000 7FFFFF No decode
; SRAM 0x800000 0xBFFFFF 1ws decoded external memory
; USER_R 0xC00000 0xDFFFFF > Read access
; USER_W 0xC00000 0xDFFFFF > Write access
; USER_X 0xC00000 0xDFFFFF > Read or Write access
; HPI(asynch) 0xE00000 0xEFFFFF DSP access to bus w/o host lock
; HPI(host locked) 0xF00000 0xFFFFFF Must pulse HPIS to advance DSP state
;
SIMULATION
TRACE_ON CLK HPIS STRB HPIA READY INT2 T0 T1 DEMO RW USERX UBOOT SRAM USERR USERW
;
; Simulate access outside decoded range
()
Note:
The simulation vectors are omitted for clarity and brevity.