SVGEN
DQ
MACRO
IPARK
MACRO
Valpha
Vbeta
Tb
Ta
Tc
Ipark_d
VdTesting
VqTesting
Theta
Ipark_q
rmp_freq
rmp_out
RG
MACRO
rmp_offset
rmp_gain
RC
MACRO
trgt_value
set_value
eq. flag
watch window
Mfunc_c1
Mfunc_c2
Mfunc_c3
PWM1A
PWM
DRV
MACRO
PWM1B
PWM2A
PWM2B
PWM3A
PWM3B
EV
HW
Dlog 1
Dlog 2
Dlog 3
Dlog 4
DLOG
MACRO
Tb
Ta
Tc
DacPtr 4
DacPtr 3
DacPtr 2
DacPtr 1
DAC 1
DAC 2
DAC 4
DAC 3
PWMDAC
MACRO
Tb
Ta
Tc
Tb-Tc
C
R
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bus voltage. The inverter phase voltage dividers and waveform monitoring filters enable the generation
of the waveform. This circuit is used to observe the low-pass filtered phase voltage waveform to make
sure that the inverter stage is working properly.
Figure 14. Build Level I - Checking Vital Signs
2.4.2
Open Loop Motor Operation - Build Level 2
In this level, the motor is connected to the inverter and the motor is run open loop. In this level, the items
below will be verified:
•
Open loop test: This is the first level that the motor is connected and run open loop. The user expects
to set VdTesting (a software variable which is supposed to generate the Vd and indirectly id
component of the stator current that produce flux) to zero since the flux will already be generated by
magnets, and apply non-zero VqTesting to generate torque. At this point, the motor should spin
smoothly, indicating that the inverter hardware is functioning properly. Since the field is not perfectly
oriented and the current loops are not closed, it is not recommended to load the motor or run it various
speeds at this level in order not to lose synchronization or stall the motor. Second, the test should
initially be run under modest dc bus level for safety reasons. Once the user confirms that everything
performs as expected, then the dc bus can be increased to the rated value. During the open loop tests,
VqTesting, SpeedRef (speed reference) and DC Bus voltages should be adjusted carefully for PM
motors so that the generated Bemf is lower than the average voltage applied to motor winding. This
will prevent the motor from stalling or vibrating. Therefore, tuning might be needed for VqTesting and
SpeedRef for different motors.
•
Verify and calibrate the ADCs measurements and check ADC configuration: It is necessary to
make sure that the scaling factors of ADC measurements (voltage, current etc.) are set correctly, and
that the dc offset caused by the passive component tolerances is minimized. Note especially that low
power motors draw low amplitude current after closing the speed loop under no-load. The performance
of the sensored/sensorless control algorithms becomes prone to phase current offset which might stop
the motor or cause unstable operation. Therefore, the phase current offset values need to be
minimized at this step. Since the current drawn by the motor is non-zero, the user should be able to
monitor the current waveforms both from PMWDAC and CCS graph windows. If the current waveforms
cannot be monitored even though the motor spins, then the ADC configuration settings should be
double checked (such as channel selection, ADC system clock enable, etc.).
•
Check the Clarke transform & current waveforms: With the motor running in a stable state, it is
possible to validate the current measurement feedback path. The peripheral driver ILEG2_DRV helps
the user configure ADC and measure 2 inverter leg currents and reconstructs the motor phase
currents. The 120o phase currents are transformed to 90o quadrature currents by the CLARK
transform module. Using PWMDAC or graph window, the shape, phase and quality of the current
waveforms can be inspected. The Clarke alpha component should be leading Clarke beta if everything
is set correctly, otherwise the user will not be able to run the next level and close the current loop.
18
TMS320C2000 Motor Control Primer
SPRUGI6 – September 2010
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