LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N
N
N N
N
N N
N
-
3
3
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
LD(n)
LD (n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
4
3
2
5
1
0
-
1
4
3
2
5
1
0
N
N
N
-
1
5
RD(n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
LD(n)
LD(n+1)
WORD
CLOCK
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
2
1
0
3
-
1
-
2
N N N
N N N
N N N
-
3
3
RD (n)
LEFT CHANNEL
RIGHT CHANNEL
LD(n) = n'th sample of left channel data
RD(n) = n'th sample of right channel data
Audio Digital I/O Interface
2.6.3 I
2
S Mode
The Audio Interface of the TLV320DAC3203 can be put into I
2
S Mode by programming Page 0, Register
27, D(7:6) = to 00. In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit
clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second
rising edge of the bit clock after the rising edge of the word clock.
Figure 2-38. Timing Diagram for I
2
S Mode
Figure 2-39. Timing Diagram for I
2
S Mode with offset=2
Figure 2-40. Timing Diagram for I
2
S Mode with offset=0 and bit clock invert
For I
2
S mode, the number of bit-clocks per channel should be greater than or equal to the programmed
word-length of the data. Also the programmed offset value should be less than the number of bit-clocks
per frame by at least the programmed word-length of the data.
59
SLAU434 – May 2012
TLV320DAC3203 Application
Copyright © 2012, Texas Instruments Incorporated
