Texas Instruments TLV320DAC26EVM, Руководство пользователя

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Program Description
3-11 Operation
3.5.2 DAC Configuration Screen
The audio DAC functions of the DAC26 can be accessed using the DAC
Configuration screen as shown in Figure 3−3.
Figure 3−3. DAC Configuration Screen
3.5.2.1 Audio PLL Section
On the DAC26, there is an on-chip phase-locked loop (PLL). The PLL can be
enabled or disabled, based on the given master clock (MCLK) to the DAC26
and the required reference frequency (FSref) for the codec. For more details
on the PLL, see the DAC26 data sheet.
With the EVM board, the MCLK is at 11.2896 MHz, and the codec sample rate
is also fixed at 44.1 kHz. So no PLL is necessary.
With the DAC26EVM, changing the PLL setting may cause audio
output distortions.