TLV320AIC3109EVM Software
19
SLAU738 – September 2017
Copyright © 2017, Texas Instruments Incorporated
TLV320AIC3109EVM-K
4.6
Clocks Tab
The TLV320AIC3109-Q1 provides a phase-locked loop (PLL) that allows flexibility in the clock generation
for the ADC and DAC sample rates. The
Clocks
tab contains the controls used to configure the
TLV320AIC3109-Q1 for operation with a wide range of master clocks. See the
Audio Clock Generation
Processing
figure in
TLV320AIC3109-Q1 Automotive, Low-Power, 96-kHz, Mono Audio Codec
for further
details of selecting the correct clock settings.
For use with the PC software and the USB-MODEVM, the clock settings must be set a certain way. If the
settings are changed from the default settings which allow operation from the USB-MODEVM clock
reference, the EVM settings can be restored automatically by pushing the
Load EVMS Clock Settings
button at the bottom of this tab. Note that changing any of the clock settings from the values loaded when
this button is pushed may result in the EVM not working properly with the PC software or USB interface. If
an external audio bus is used (audio not driven over the USB bus), then settings may be changed to any
valid combination. The
Clocks
tab is shown in
Figure 12. Clocks Tab
4.6.1
Configuring the Codec Clocks and Fsref Calculation
The codec clock source is chosen by the
CODEC_CLK Source
control. When this control is set to
CLKDIV_OUT
, the PLL is not used; when set to
PLLDIV_OUT
, the PLL is used to generate the clocks.
NOTE:
Per
TLV320AIC3109-Q1 Automotive, Low-Power, 96-kHz, Mono Audio Codec
, the codec
should be configured to allow the value of Fsref to fall between the values of 39 kHz to
53 kHz.
