Texas Instruments TLV320AIC10 EVM, Руководство пользователя

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EVM Operation Modes
3-2
3.1 EVM Operation Modes
TLV320AIC10/11 devices have two operation modes, master or slave. The
device is a master device if it generates the shift clock (SCLK) and frame sync
signal (FS) and sends them to slave devices. A slave device uses external
SCLK and FS signals.
The TLV320AIC10/11 EVM board is populated with two TLV320AIC10/11
devices and has footprints and basic circuits for six more such devices. The
two populated AIC10/11s (U1 and U2) can be configured as two separate
masters or slaves to interface with the McBSP0 and McBSP1 on
TMS320C5402 DSK. The separate master/slave operation modes are shown
in Table 3–1. The devices can also be cascaded to connect to McBSP0, as is
shown in Table 3–2.
Table 3–1. Separate Operation Modes
McBSP0 McBSP1 AIC10/11 U1 AIC10/11 U2
Master — Slave —
Slave — Master —
— Master — Slave
— Slave — Master
Table 3–2. Cascaded Operation Modes
McBSP0 AIC10/11 U1 AIC10/11 U2
AIC10/11 U3 to U8
(not populated)
Master Slave Slave Slave(s)
Slave Master Slave Slave(s)
By EVM design, AIC10/11 device U1 interfaces with McBSP0 only, and can be
configured as a master or slave of McBSP0. Device U2 interfaces with both
McBSP0 and McBSP1. U2 can be configured as a master or slave of McBSP1,
or as a slave of U1 interfacing with McBSP0. Setup of the onboard jumpers is
required for proper operation.
3.1.1 AIC10/11 Master Mode
A TLV320AIC10/11 device is configured as a master if the M/S pin of the device
is pulled high. The master device generates the SCLK and FS.
If the number of cascaded AIC10/11 = 1 to 4: Frequency of SCLK = MCLK/N
If the number of cascaded AIC10/11 devices = 5 to 8:
Frequency of SCLK = 2*MCLK/N
Where frequency divider N = 1, 2, .
…
32.
The frequency divider is programmable and is defined in AIC10/11 control
register CR2. The powerup default value is 32.