Texas Instruments TLV320AIC10 EVM, Руководство пользователя

Страница: 28 / 53

Host Interface
4-4
Figure 4–2. C540x DSP McBSP and AIC10/11 Interface
FSX
FSR
CLKX
CLKR
DTx
DRx
CLKOUT
If AIC is Master
FS
SCLK
DIN
DOUT
DCSI
FSD
MCLK
If AIC is Slave
TMS320C54xx TLV320AIC10/11 From Host
To Other AIC10/11s’ DCSI
To Next Slave AIC10/11
MCLK
Selection
From Crystal Oscillator
From External Clock
DOUT
DIN
SCLK
MCLK
To All AIC10/11s
FS
4.2.2 Host Interface
The host interface on the AIC10/11 EVM is primarily designed for the AIC de-
vice direct configuration. When direct configuration of the AIC control registers
via the DCSI pin is used, jumper W20 selects the serial data input source from
either the motherboard DSK McBSP1 or from an external source.
4.2.3 MCLK Selection
The AIC10/11 EVM contains an onboard crystal oscillator that generates an
8.2 MHz clock. Installing jumper W14 to position 2–3 selects the onboard
oscillator as the master clock source (MCLK) for onboard CODEC devices.
Also, the DSP system clock (CLKOUT, at the
½
CPU frequency) is brought
onboard the EVM from the motherboard through J10. Installing W14 to
position 1–2 selects CLKOUT as MCLK source. An external clock source can
be used as MCLK by removing jumper W14 and connecting the external clock
to pin 2 (center pin) of W14.
4.2.4 AIC10/11 Device Digital Configuration
Operation and mode of the two TLV320AIC10/11 devices (U1 and U2) can be
configured through the
digital signal configuration and controls circuits. Refer
to Figure 1–2 EVM Block Diagram in Chapter 1.
The digital signal configuration and controls circuits contain the jumper
configurations that determine master/slave and separate/cascade operation
mode. Other basic setup and configuration circuits, including the frame sync
mode configuration circuit, reset generation circuit, and power-down
generation circuit
, are also used. These mode and circuit configurations are
discussed in Chapter 3,
Operation Modes.