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3-6

3.2.2

SRC4194 Software Mode Configuration Via The Host Port

In Software mode, the SRC4194 relies upon an external host device to pro-
gram the internal control registers via the four-wire SPI port. The SPI port is
accessed using the Host Port header, connector J1. The header is buffered
by U2, an octal buffer IC with tri-state outputs. The buffer outputs are enabled
only when the H/S element of switch SW2 is set to the LO state. When H/S is
HI, the buffer outputs are set to a high-impedance state.

The Host Port header provides a convenient interface point for connection to
an external host device, such as a microprocessor, a digital signal controller/
processor, or a digital input/output card installed in a PC.

Refer to the SRC4194 datasheet for a description of the SPI port protocol and
control register definitions.

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Содержание SRC4194EVM

Страница 1: ... July 2004 User s Guide SBAU096 ...

Страница 2: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Страница 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Страница 4: ...ncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 70 C The EVM is designed to operate properly with certain components above 70 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass tran...

Страница 5: ...the term EVM and the phrase evaluation module are synonymous with the SRC4194EVM Chapter 1 provides a product overview for the SRC4194 four channel asyn chronous sample rate converter The SRC4194EVM block diagram and pri mary features are also discussed Chapter 2 provides general information regarding EVM handling and unpack ing as well as absolute operating conditions for power supplies and input...

Страница 6: ...contains cautions The information in a caution is provided for your protection Please read each caution carefully This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment ...

Страница 7: ...00 477 8924 or the Product Information Center at 972 644 5580 When ordering identify the document s by both title and literature number Data Sheets Literature Number SRC4194 SBFS025A DIT4192 SBOS229B PLL1705 SLES046A REG1117 SBVS001B SN74ALVC125 SCES110E SN74ALVC244 SCES188B SN74ALVC245 SCES271B SN74LVC1G04 SCES214M SN74LVC1G08 SCES217L SN74LVC244A SCAS414U Additional Documentation The following d...

Страница 8: ...est environment only It may generate use or radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to sub part J of part 15 of the FCC regulations which are designed to provide reasonable protec tion against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in ...

Страница 9: ...mum Operating Conditions 2 4 3 Hardware Description and Configuration 3 1 3 1 Power Supply Configuration 3 2 3 2 SRC4194 Configuration Modes 3 4 3 2 1 SRC4194 Hardware or Standalone Mode Configuration 3 4 3 2 2 SRC4194 Software Mode Configuration Via The Host Port 3 6 3 3 Audio Input Ports 3 7 3 4 Audio Output Ports 3 8 3 5 Reference Clock Generation 3 10 3 6 TDM Test Mode 3 11 4 Schematic PCB Lay...

Страница 10: ...ematic Diagram Page 2 of 2 4 4 4 3 Top Side Silk Screen 4 5 4 4 Bottom Side Silk Screen 4 6 4 5 Top Layer Component Side 4 7 4 6 Ground Plane Layer 4 8 4 7 Power Layer 4 9 4 8 Bottom layer Solder Side 4 10 2 1 Absolute Operating Conditions 2 4 3 1 Common Configurations using a 5V Supply and an Optional EXT VIO Supply 3 3 3 2 Setting the Configuration Mode 3 4 3 3 Hardware Mode Setup Matrix Using S...

Страница 11: ...r channel audio asynchronous sample rate converter as well as a general description and feature list for the SRC4194EVM Topic Page 1 1 SRC4194 Product Overview 1 2 1 2 SRC4194 Functional Block Diagram 1 3 1 3 SRC4194EVM Features 1 5 1 4 SRC4194EVM Functional Block Diagram 1 6 Chapter 1 ...

Страница 12: ...de In Master mode the LRCK and BCK clocks are derived from the refer ence clock inputs either RCKIA or RCKIB The flexible configuration options for the input and output ports allows connection to a variety of audio data con verters digital audio interface devices and digital signal processors A bypass mode is included which allows audio data to be passed directly from the input port to the output ...

Страница 13: ... to the re sampler The rate estimator compares the input and output sampling frequencies by comparing LRCKI LRCKO and a reference clock The results of the rate estimation are used to configure the re sampler coefficients and data pointers The output of the re sampler is passed on to either the decimation filter or direct down sampler function The decimation filter performs down sampling and antial...

Страница 14: ... MUTEB Control SRC B SPI Port and Reset IFMTB0 IFMTB1 IFMTB2 OFMTB0 OFMTB1 OWLB0 OWLB1 BYPB H S RST VIO DGND VDD18 2 VDD33 2 DGND REGEN LRCKIA BCKIA SDINA RCKIA Input Serial Port Digital De Emphasis and Interpolation Filters Re Sampler Digital Decimation Filter Output Serial Port LRCKOA BCKOA SDOUTA TDMIA Rate Estimator fsOUT RDYB fsIN RATIOB LRCKIB BCKIB SDINB RCKIB Input Serial Port Digital De E...

Страница 15: ...rd voltage regula tors or external supplies Buffered input and output serial ports support connection to external hard ware and test systems Two 75Ω AES3 inputs with onboard receivers supporting input sampling rates up to 108kHz Two 75Ω AES3 outputs supporting sampling rates up to 192kHz Flexible SRC reference clock generation using onboard PLL circuitry or external clock sources Supports hardware...

Страница 16: ...ration details for the various hardware func tions included on the EVM board Figure 1 2 SRC4194EVM Functional Block Diagram AES3 Tx DIT4192 AES3 Tx DIT4192 AES3 Rx CS8414 AES3 Rx CS8414 PORT BUFFERS PORT BUFFERS PORT BUFFERS PORT BUFFERS SW8 SW8 SW6 SW6 H D R H D R H D R H D R AES OUT B AES OUT A AES IN B AES IN A OUTPUT PORT B OUTPUT PORT A INPUT PORT B INPUT PORT A SW4 SW5 SW10 SW10 SW1 SW2 4 CH...

Страница 17: ...ovides information regarding SRC4194EVM handling and unpacking as well as absolute operating conditions Topic Page 2 1 Electrostatic Discharge Warning 2 2 2 2 Unpacking the EVM 2 3 2 3 Absolute Maximum Operating Conditions 2 4 Chapter 2 ...

Страница 18: ...nts Many of the components on the SRC4194EVM are susceptible to damage by electrostatic discharge ESD Customers are advised to observe proper ESD handling procedures when unpacking and handling the EVM including the use of a grounded wrist strap at an approved ESD workstation Failure to ob serve ESD handling procedures may result in damage to EVM components ...

Страница 19: ... check to make sure that the following items are included One SRC4194EVM One printed copy of the SRC4194 data sheet One printed copy of the SRC4194EVM User s Guide If any of these items are missing please contact the Texas Instruments Prod uct Information Center nearest you to inquire about replacements ...

Страница 20: ...nd possibly the equipment connected to it Table 2 1 summarizes the critical data points Table 2 1 Absolute Operating Conditions MIN MAX UNIT Power Supplies 5V 4 5 6 0 V EXT 1 8V 1 65 2 0 V EXT 3 3V 3 0 3 6 V EXT VIO 1 1 65 3 6 V Input Port A and B Output Port A and B Host Port SRC A and B EXT Clock and DIT Clock A and B 1 VIH VIO 0 3 V VIL 0 3 V AES IN A and B Ports VIH 7 0 V VIL 0 5 V 1 VIO may b...

Страница 21: ...SRC4194EVM Topic Page 3 1 Power Supply Configuration 3 2 3 2 SRC4194 Configuration Modes 3 4 SRC4194 Hardware or Standalone Mode Configuration 3 4 SCR4194 Software Mode Configuration Via The Host Port 3 6 3 3 Audio Input Ports 3 7 3 4 Audio Output Ports 3 8 3 5 Reference Clock Generation 3 10 3 6 TDM Test Mode 3 11 Chapter 3 ...

Страница 22: ...ply Configuration and Jumpers 5V GND GND 1 8V 3 3V EXT VIO EXT VIO EXT 1 8V EXT 3 3V 5V REG 3 3V U33 U32 3 3V REG 1 8V REG REG 1 8V REG 1 8V REG 3 3V VIO 6 5 4 3 2 1 J14 J15 REG 3 3V VDD33 J16 REG 1 8V EXT 1 8V EXT 3 3V EXT VIO VDD18 J17 NC 1 NC 1 NOTE 1 NC not connected Referring to Figure 3 1 the SRC4194EVM includes two onboard linear volt age regulators U32 and U33 which are used to derive 1 8V...

Страница 23: ...gulator U33 REG 1 8V 2 Core Voltage 1 8V using onboard regulator U33 NC REG 1 8V LO 2 VIO 3 3V using onboard regulator U32 REG 3 3V 3 Core Voltage 3 3V using onboard regulator U32 REG 3 3V NC HI 3 VIO 3 3V using onboard regulator U32 REG 3 3V 4 Core Voltage 1 8V using onboard regulator U33 NC REG 1 8V LO 4 VIO 1 65V to 3 6V using EXT VIO supply EXT VIO 5 Core Voltage 3 3V using onboard regulator U...

Страница 24: ...set the dedicated control pins to either a low or high logic level The switches corre spond one to one with the pin names of the SRC4194 device Table 3 3 sum marizes the switch functions and available settings for each element of switch SW1 SW2 SW4 and SW5 In addition to the switches already mentioned a momentary pushbutton switch SW3 is used for the SRC4194 reset function The RST input pin 21 of ...

Страница 25: ...bits HI HI 16 bits Bypass Mode LO Disabled HI Enabled Interpolation Filter Group Delay LO LO Buffer 64 samples before resampling HI LO Buffer 32 samples before resampling LO HI Buffer 16 samples before resampling HI HI Buffer 8 samples before resampling Decimation Mode LO Decimation Filter Enabled HI Direct Downsampling Enabled De Emphasis Filter Function LO LO Disabled HI LO Enabled for fs 48kHz ...

Страница 26: ...r IC with tri state outputs The buffer outputs are enabled only when the H S element of switch SW2 is set to the LO state When H S is HI the buffer outputs are set to a high impedance state The Host Port header provides a convenient interface point for connection to an external host device such as a microprocessor a digital signal controller processor or a digital input output card installed in a ...

Страница 27: ...ctors accept 75Ω coaxial cable connections terminated with RCA plugs The onboard AES3 receivers U14 and U24 recover audio clocks and data from the AES3 encoded input stream The receivers are configured to output 24 bit I2S formatted audio data with a serial bit or data clock rate of 64fs and a left right word clock rate of fs where fs is the frame or sampling rate of the incoming AES3 formatted da...

Страница 28: ...AES3 transmit ters U7 and U17 provide the AES3 encoded data streams for each output Both transmitters are configured to accept 24 bit I2S formatted audio data at sampling rates up to 192kHz The AES OUT A and B output ports provide a convenient standard interface to consumer and professional audio equip ment as well as common audio test systems Figure 3 3 Output Port External Connections and Config...

Страница 29: ...time division multiplexed TDM formatted audio data with word lengths up to 24 bits and sampling rates up to 212kHz The output ports may be operated in either Slave or Master mode but must match the output port setup for the SRC4194 device as de fined in Table 3 3 The buffered serial output ports provide a convenient meth od for interfacing to audio devices which support an audio serial data interf...

Страница 30: ...f the EVM and are made available at the audio input and output ports for use by external hard ware Figure 3 4 Reference Clock Generation Connections and Configuration Switch SW10 A_PLL LO Use PLL U25 HI Use Ext Clock J12 Switch SW10 A_FS1 A_FS2 A_SR SCKO2 To RCKIA SRC A EXT CLOCK J12 FS1 FS2 SR U25 PLL1705DBQ Switch SW10 B_PLL LO Use PLL U28 HI Use Ext Clock J13 Switch SW10 B_CLK LO Use PLL or EXT...

Страница 31: ...is provided to allow a simple onboard connection between SDOUTA pin 64 and TDMIB pin 52 This provides a test mode for evaluating the TDM output data format When J18 is shorted the TDMIB pin at header J7 should be floating with no external connection ...

Страница 32: ...3 12 ...

Страница 33: ... chapter provides the electrical schematic and physical layout information for the SRC4194EVM The bill of materials is included for component and manufacturer reference Topic Page 4 1 Schematic 4 2 4 2 PCB Layout 4 5 4 3 Bill of Materials 4 11 Chapter 4 ...

Страница 34: ...Schematic 4 2 4 1 Schematic The electrical schematic for the SRC4194EVM is shown in Figure 4 1 and Figure 4 2 Descriptions of the components shown on the schematics are listed in Table 4 1 ...

Страница 35: ...3 14 A4 8 Y4 12 VCC 20 GND 10 U6A SN74ALVC244PW G 19 A1 11 Y1 9 A2 13 Y2 7 A3 15 Y3 5 A4 17 Y4 3 U6B SN74ALVC244PW CSS 1 COPY C 2 L 3 CLK1 4 CLK0 5 MCLK 6 VIO 7 DGND 8 FMT0 9 FMT1 10 SCLK 11 SYNC 12 SDATA 13 M S 14 MODE 28 U 27 V 26 BLS 25 BLSM 24 EMPH 23 AUDIO 22 MONO 21 MDAT 20 VDD 19 TX 18 TX 17 DGND 16 RST 15 U7 DIT4192IPW 1 2 4 5 3 U8 SN74LVC1G08DBV 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 3Y 8 ...

Страница 36: ...F 5V 5V D6 LOCK B R18 475 5V R19 475 C73 0 068uF RN20 100 2 4 6 1 3 5 7 8 9 10 J10 INPUT PORT B VIO C57 0 1uF VIO C58 0 1uF G 1 A1 2 Y1 18 A2 4 Y2 16 A3 6 Y3 14 A4 8 Y4 12 VCC 20 GND 10 U23A SN74LVC244APW C70 0 1uF VIO 2 4 5 3 U27 SN74LVC1G04DBV 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 3Y 8 3A 9 3OE 10 4Y 11 4A 12 4OE 13 VCC 14 U26 SN74ALVC125PW VDD1 1 SCKO2 2 SCKO3 3 DGND1 4 FS1 5 FS2 6 SR 7 VCC 8 A...

Страница 37: ...uit board PCB with the following layer structure Layer 1 Top Component Side Layer 2 Ground Plane Layer 3 Power Layer 4 Bottom Solder Side Figure 4 3 through Figure 4 8 show the top side silk screen along with the top ground plane power and bottom layers of the printed circuit assembly Figure 4 3 Top Side Silk Screen ...

Страница 38: ...PCB Layout 4 6 Figure 4 4 Bottom Side Silk Screen ...

Страница 39: ...PCB Layout 4 7 Schematic PCB Layout and Bill of Materials Figure 4 5 Top Layer Component Side ...

Страница 40: ...PCB Layout 4 8 Figure 4 6 Ground Plane Layer ...

Страница 41: ...PCB Layout 4 9 Schematic PCB Layout and Bill of Materials Figure 4 7 Power Layer ...

Страница 42: ...PCB Layout 4 10 Figure 4 8 Bottom layer Solder Side ...

Страница 43: ... X7R Ceramic 0 1µF 10 16WV Size 0603 5 10µF C8 C22 C78 C81 19 Kemet T491A106K010AS Chip Capacitor Tantalum 10µF 10 10WV Size A 6 100µF C82 C85 4 Kemet T491D107K010AS Chip Capacitor Tantalum 100µF 10 10WV Size D 7 J1 J2 J5 J7 J10 5 Samtec TSW 105 07 G D Terminal Strip 10 pin 5x2 8 J3 J6 J8 J11 4 CUI Stack RCJ 041 RCA Jack PC Mount Black 9 J4 J9 J12 J13 4 Kings Electronics KC 79 274 M06 BNC Connecto...

Страница 44: ...sistors 21 10kΩ RN2 RN4 RN6 RN8 RN10 RN11 RN12 7 CTS 741X163103JCT ND Thick Film Chip Resistor Array 10kΩ 16 terminal 8 resistors 22 10kΩ RN3 RN5 RN7 RN9 RN13 5 CTS 741X083103JCT ND Thick Film Chip Resistor Array 10kΩ 8 terminal 4 resistors 23 SW1 SW2 SW4 SW5 5 ITT C K Switch TDA10H0SK1 DIP Switch 10 Position Half Pitch Surface Mount Tape Sealed 24 SW6 SW8 2 ITT C K Switch TDA08H0SK1 DIP Switch 8 ...

Страница 45: ...VC125PW Quad Buffer with Tri State Outputs 33 U13 U23 2 Texas Instruments SN74LVC244APW Octal Buffer Driver with Tri State Outputs 34 U14 U24 2 Cirrus Logic CS8414 CS 96kHz Digital Audio Interface Receiver 35 U25 U28 2 Texas Instruments PLL1705DBQ Dual PLL Multiclock Generator 36 U32 1 Texas Instruments REG1117 3 3 3 3V Linear Voltage Regulator 37 U33 1 Texas Instruments REG1117A 1 8 1 8V Linear V...

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