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SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 www.ti.com
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Peripheral Information and Timings
Copyright © 2011–2016, Texas Instruments Incorporated
7.12.1.2 McSPI—Master Mode
Table 7-83. McSPI Timing Conditions – Master Mode
PARAMETER
LOW LOAD HIGH LOAD
UNIT
MIN MAX MIN MAX
Input Conditions
t
r
Input signal rise time 8 8 ns
t
f
Input signal fall time 8 8 ns
Output Condition
C
load
Output load capacitance 5 25 pF
Table 7-84. Timing Requirements for McSPI Input Timings – Master Mode
(see Figure 7-90 )
NO.
OPP100 OPP50
UNIT LOW LOAD HIGH LOAD LOW LOAD HIGH LOAD
MIN MAX MIN MAX MIN MAX MIN MAX
4
t
su(SOMI-
SPICLKH)
Setup time, SPI_D[x] (SOMI) valid before
SPI_CLK active edge
(1)
2.29 3.02 2.29 3.02 ns
5
t
h(SPICLKH-
SOMI)
Hold time, SPI_D[x]
(SOMI) valid after
SPI_CLK active edge
(1)
Industrial extended
temperature
(-40°C to 125°C)
7.1 7.1 7.1 7.1
ns
All other
temperature ranges
4.7 4.7 4.7 4.7
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 7-85. Switching Characteristics for McSPI Output Timings – Master Mode
(see Figure 7-91 )
NO. PARAMETER
OPP100 OPP50
UNIT LOW LOAD HIGH LOAD LOW LOAD HIGH LOAD
MIN MAX MIN MAX MIN MAX MIN MAX
1 t
c(SPICLK)
Cycle time, SPI_CLK 20.8 20.8 41.6 41.6 ns
2 t
w(SPICLKL)
Typical pulse duration,
SPI_CLK low 0.5P –
1.04
(1)
0.5P +
1.04
(1)
0.5P –
2.08
(1)
0.5P +
2.08
(1)
0.5P –
1.04
(1)
0.5P +
1.04
(1)
0.5P –
2.08
(1)
0.5P +
2.08
(1)
ns
3
t
w(SPICLKH)
Typical pulse duration,
SPI_CLK high 0.5P –
1.04
(1)
0.5P +
1.04
(1)
0.5P –
2.08
(1)
0.5P +
2.08
(1)
0.5P –
1.04
(1)
0.5P +
1.04
(1)
0.5P –
2.08
(1)
0.5P +
2.08
(1)
ns
t
r(SPICLK)
Rising time, SPI_CLK 3.82 3.82 3.82 3.82 ns
t
f(SPICLK)
Falling time, SPI_CLK 3.44 3.44 3.44 3.44 ns
6 t
d(SPICLK-SIMO)
Delay time, SPI_CLK
active edge to SPI_D[x]
(SIMO) transition
(2)
–3.57 3.57 –4.62 4.62 –3.57 3.57 –4.62 4.62 ns
7 t
d(CS-SIMO)
Delay time, SPI_CS active
edge to SPI_D[x] (SIMO)
transition
(2)
3.57 4.62 3.57 4.62 ns
8 t
d(CS-SPICLK)
Delay time,
SPI_CS active
to SPI_CLK
first edge
Mode 1
and 3
(3)
A – 4.2
(4)
A – 2.54
(4)
A – 4.2
(4)
A – 2.54
(4)
ns
Mode 0
and 2
(3)
B – 4.2
(5)
B – 2.54
(5)
B – 4.2
(5)
B – 2.54
(5)
ns
9 t
d(SPICLK-CS)
Delay time,
SPI_CLK last
edge to
SPI_CS
inactive Mode 1
and 3
(3)
B – 4.2
(5)
B – 2.54
(5)
B – 4.2
(5)
B – 2.54
(5)
ns
Mode 0
and 2
(3)
A – 4.2
(4)
A – 2.54
(4)
A – 4.2
(4)
A – 2.54
(4)
ns
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).