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3.2
Analog Inputs
3.3
Audio Data Format Selection
Hardware Description and Configuration
The PCM4202EVM includes two Neutrik combo XLR connectors, which accept either 3-pin male
XLR or ¼-inch TRS phono plugs. The connectors are numbered J1 and J2, corresponding to the
left and right channels, respectively.
The analog inputs can accept up to a 7.9V
RMS
(or 22.3V
PP
) differential input signal. This signal is
then attenuated by a factor of 3.7 by the input buffer circuit, which corresponds to the 6.0V
PP
full-scale differential input voltage for the PCM4202 analog inputs.
The input buffer circuits are each comprised of a single OPA1632 fully differential audio amplifier
and associated passive components. The input buffer provides active attenuation and low pass
filtering for the analog input signal. The OPA1632 outputs are DC level-shifted by approximately
+2.5V using the amplifiers V
COM
IN input (pin 2), which are connected to a buffered version of either
the PCM4202 V
COM
L (pin 3) or V
COM
R outputs (pin 26).
Switch SW1 is used to select the audio data format for the PCM4202.
Table 2
summarizes the
available audio data formats for both Slave and Master mode operation and the corresponding
SW1 switch settings.
Table 2. Audio Data Format Selection
FMT1
FMT0
Audio Data Format (Slave or Master Mode)
LO
LO
24-Bit Left Justified PCM Data
LO
HI
24-Bit I
2
S PCM Data
HI
LO
24-Bit Right Justified PCM Data
HI
HI
DSD Output Mode (Master Mode only)
PCM4202EVM User's Guide
SBAU103–August 2004
9
Master mode may also be configured to support 1-bit DSD-formatted audio output data, as shown
in
Table 2
. For the DSD mode formats, header J4 provides the output interface. The DATA output
functions as the RIght channel DSD output (DSDR), the BCK output servers as the left channel
DSD output (DSDL), and the LRCK output becomes the DSD bit clock (DSDBCK).
For Slave mode operation, the Audio Serial Port header (connector J4) is utilized to interface to a
Master device, such as a digital signal processor, FPGA, or an audio test system with a
synchronous serial port interface. The system clock (SCKI), bit clock (BCK), and left/right word
clock (LRCK) are generated by the Master device and are used to drive the SCKI (pin 18), BCK
(pin 16), and LRCK (pin 17) inputs of the PCM4202. Serial audio data is output at DATA (pin 15).
Slave mode supports PCM-formatted output data only. DSD output data is available only in
Master mode.
For Master mode, the system clock is provided by one of the sources described in Section 3.4 of
this document. The PCM4202 internally generates the BCK and LRCK clocks, which are then
output to the Audio Serial Port header (connector J4) and the AES3 digital interface transmitters,
which then drive output connectors J5 and J6.
