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L4 Interconnects
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9.3.2 L4 Interconnects Integration
9.3.2.1 Clocking, Reset, and Power-Management Scheme
9.3.2.1.1 Clocks
Four functional clocks are used in each L4 interconnect (see Table 9-110 ).
Table 9-110. L4 Interconnect Clocks
Clock Frequency Name Comments
L4-Core interconnect clock Up to Core_L3_ICLK/2 CORE_L4_GICLK Source, control, and gating handled by PRCM
module
L4-Per interconnect clock Up to Core_L3_ICLK/2 PER_L4_GICLK Source, control, and gating handled by PRCM
module
L4-Emu clock L4_EMU Clock for emulation
L4-Wakeup interconnect WKUP_L4_GICLK Source, control, and gating handled by PRCM
clock module
9.3.2.1.2 Resets
9.3.2.1.2.1 Hardware Reset
L4 interconnects receive a reset signal from the PRCM module, which is the reset signal to the CORE
power domain. For more details, see Power, Reset, and Clock Management.
Table 9-111 lists the hardware reset for the L4-Core interconnect.
Table 9-111. L4 Interconnect Hardware Reset
Interconnect Reset Domain
L4-Core interconnect CORE_RST
L4-Per interconnect PER_RST
L4-Wakeup interconnect WKUP_RST
L4-Emu interconnect EMU_RST
9.3.2.1.2.2 Software Reset
The L4 interconnects have hardware reset capabilities, but do not have software reset capabilities. The
hardware reset capabilities are controlled by the PRCM module and are applied to the L4 interconnects
and the connected L4 TAs and L4 target modules.
9.3.2.1.3 Power Domain
For more details on power voltage scaling, seePower, Reset, and Clock Management.
Table 9-112 lists the power domains for the L4-Core and L4-Wakeup interconnects.
Table 9-112. L4 Interconnect Power Domains
Interconnect Power Domain
L4-Core interconnect CORE
L4-Per interconnect PER
L4-Emu interconnect EMU
L4-Wakeup interconnect WKUP
2060 Interconnect SWPU177N – December 2009 – Revised November 2010
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