Texas Instruments MSP430F6735A, Руководство пользователя

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2. When accessing the DMA address registers, enable the Read Modify Write disable bit
(DMARMWDIS = 1) or temporarily disable all active DMA channels (DMAEN = 0).
OR
3. Use word access for accessing the DMA address registers. Note that this limits the
values that can be written to the address registers to 16-bit values (lower 64K of Flash).
DMA7
DMA Module
Category
Functional
Function DMA request may cause the loss of interrupts
Description If a DMA request starts executing during the time when a module register containing an
interrupt flags is accessed with a read-modify-write instruction, a newly arriving interrupt
from the same module can get lost. An interrupt flag set prior to DMA execution would not
be affected and remain set.
Workaround 1. Use a read of Interrupt Vector registers to clear interrupt flags and do not use read-
modify-write instruction.
OR
2. Disable all DMA channels during read-modify-write instruction of specific module
registers containing interrupts flags while these interrupts are activated.
DMA9
DMA Module
Category
Functional
Function DMA stops transferring bytes unexpectedly
Description When the DMA is configured to transfer bytes from the eUSCI_A or eUSCI_B transmit
or receive buffers, the transmit or receive triggers (TXIFG and RXIFG) may not be seen
by the DMA module and the transfer of the bytes is missed. Once the first byte in a
transfer sequence is missed, all the following bytes are missed as well. All eUSCI_A
modes (UART, SPI, and IrDA) and all eUSCI_B modes (SPI and I2C) are affected.
Workaround 1) Use Interrupt Service Routines to transfer data to and from the eUSCI_A or eUSCI_B.
OR
2) When using DMA channel 0 for transferring data to and from the eUSCI_A or
eUSCI_B, use DMA channel 2 (lower priority than DMA channel 0) to read the same
register of the eUSCI_A or eUSCI_B that DMA channel 0 is working with. Use the same
USCI IFG (e.g. UCA0RXIFG) as trigger source for these both DMA channels.
DMA10
DMA Module
Category
Functional
Function DMA access may cause invalid module operation
Description The peripheral modules MPY, CRC, USB, RF1A and FRAM controller in manual mode
can stall the CPU by issuing wait states while in operation. If a DMA access to the
module occurs while that module is issuing a wait state, the module may exhibit undefined
behavior.
Advisory Descriptions www.ti.com
12 MSP430F6735A Microcontroller SLAZ647S – FEBRUARY 2015 – REVISED MAY 2021
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