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MSP430F663x
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SLAS566 – OCTOBER 2009
Table 7. Port Mapping, Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCB0SIMO
USCI_B0 SPI slave in master out (direction controlled by USCI)
15
PM_UCB0SDA
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0CLK
USCI_B0 clock input/output (direction controlled by USCI)
16
PM_UCA0STE
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
17
PM_MCLK
-
MCLK
18
PM_E0
EDI test pin (open drain and direction controlled by EDI)
19
PM_E1
EDI test pin (open drain and direction controlled by EDI)
20 - 30
Reserved
None
DV
SS
Disables the output driver as well as the input Schmitt-trigger to prevent parasitic cross
31 (0FFh)
(1)
PM_ANALOG
currents when applying analog signals.
(1)
The value of the PMPAP_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are
ignored resulting in a read out value of 31.
Table 8. Default Mapping
PIN
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCB0STE/PM_UCA0
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input) /
P2.0/P2MAP0
CLK
USCI_A0 clock input/output (direction controlled by USCI)
PM_UCB0SIMO/PM_UCB
USCI_B0 SPI slave in master out (direction controlled by USCI) / USCI_B0 I2C
P2.1/P2MAP1
0SDA
data (open drain and direction controlled by USCI)
PM_UCB0SOMI/PM_UCB
USCI_B0 SPI slave out master in (direction controlled by USCI) / USCI_B0 I2C
P2.2/P2MAP2
0SCL
clock (open drain and direction controlled by USCI)
PM_UCB0CLK/PM_UCA0
USCI_B0 clock input/output (direction controlled by USCI) / USCI_A0 SPI slave
P2.3/P2MAP3
STE
transmit enable (direction controlled by USCI - input)
PM_UCA0TXD/PM_UCA0 USCI_A0 UART TXD (direction controlled by USCI - output) / USCI_A0 SPI slave
P2.4/P2MAP4
SIMO
in master out (direction controlled by USCI)
PM_UCA0RXD/PM_UCA0
USCI_A0 UART RXD (direction controlled by USCI - input) / USCI_A0 SPI slave
P2.5/P2MAP5
SOMI
out master in (direction controlled by USCI)
P2.6/P2MAP6/R03
PM_NONE
-
DV
SS
P2.7/P2MAP7/LCDREF/R1
PM_NONE
-
DV
SS
3
Oscillator and System Clock
The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS)
module that includes support for a 32 kHz watch crystal oscillator (XT1 LF mode - XT1 HF mode not supported),
an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO),
an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS
module is designed to meet the requirements of both low system cost and low-power consumption. The UCS
module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator,
stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO
provides a fast turn-on clock source and stabilizes in less than 5
μ
s. The UCS module provides the following
clock signals:
•
Auxiliary clock (ACLK), sourced from a 32 kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal
digitally-controlled oscillator DCO.
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
•
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
•
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
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