Texas Instruments LMK05318EVM, Руководство пользователя

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EVM Quick Start
9 SNAU236A – June 2018 – Revised December 2018
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Copyright © 2018, Texas Instruments Incorporated
LMK05318EVM User's Guide
• Oscillators onboard:
– XO (Y1), Default: 48.0048 MHz, 3.3 V, LVCMOS, low-jitter, ±25-ppm stability
– XO (U10), Alternate: LMK61E2, 10 to 1000 MHz (I
2
C-programmable), 3.3 V, Differential, low-jitter,
±50-ppm stability
NOTE: The EEPROM image of the LMK05318 was custom programmed to demonstrate the default
configuration in Table 3 , which is different from the EEPROM image of generic factory-
programmed devices.
(1)
Clock input frequency thresholds (ppm) are relative to the frequency accuracy of the XO input.
Table 3. Default Configuration - EEPROM Start-Up Modes
DEVICE START-UP MODE
I
2
C MODE
(HW_SW_CTRL = 0)
SPI MODE
(HW_SW_CTRL = Float)
HW_SW_CTRL (JP19)
Jumper Setting
Tie pins 2-3 Tie pins 2-4 (open)
MCU I
2
C/SPI (JP20)
Jumper Settings
Tie pins 1-2, 3-4, 11-12 and 13-14
MCU I
2
C interface to DUT
Tie pins 7-8, 9-10, 11-12, and 13-14
MCU SPI interface to DUT
GPIO1/SCS (S6)
Jumper Settings
S6[1] = OFF, S6[2:3] = ON
GPIO1 = 0: I
2
C Address = 0x64h
S6[1] = OFF, S6[2:3] = ON
SPI SCS input to MCU
GPIO2/SDO/FINC (S7)
Jumper Settings
S7[1] = OFF, S7[2:3] = ON
Not used by default
S7[1] = OFF, S7[2:3] = ON
SPI SDO output to MCU
XO Input
48.0048-MHz DIFF or LVCMOS
(On-chip termination disabled)
PRIREF and SECREF Clock Inputs
25-MHz DIFF or LVCMOS
(On-chip termination disabled)
DPLL Clock Input Assignment
PRIREF, SECREF
(Highest to lowest priority order)
DPLL Clock Input Selection Manual Fallback mode with Pin Select
PLL Mode DPLL Mode with APLL2 disabled
DPLL Loop Bandwidth 100 Hz
DPLL TDC Frequency 25 MHz
APLL1 VCO Frequency 2500 MHz
APLL2 VCO Frequency n/a (APLL2 disabled)
OUT[0:1] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[2:3] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[4] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[5] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[6] Output 156.25 MHz AC-LVPECL (from APLL1)
OUT[7] Output
156.25 MHz HCSL (from APLL1)
(On-chip termination disabled)
PRIREF and SECREF
Frequency Detector Thresholds
(1)
Not Enabled
PRIREF and SECREF
Window Detector Thresholds
33.6 ns (Early) < Valid REF Input Period < 46.4 ns (Late)
DPLL Frequency Lock
Detector Thresholds
DPLL Locked < 1 ppm, DPLL Unlocked > 10 ppm
STATUS0 Output DPLL Loss of Lock (active high)
STATUS1 Output DPLL Holdover Active (active high)