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Device Under Test

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SNAU236A – June 2018 – Revised December 2018

LMK05318EVM User's Guide

Device Under Test

The evaluation module is shipped with the LMK05318 DUT (U5) soldered down. The pin 1 position of the
48-pin QFN package is indicated by a dot symbol in top silkscreen. Alternatively, the U5 can be
unmounted and a test socket (XU1) can be populated. See for the socket part number. TI recommends
populating the socket with the hinge on the left-hand side (towards OUT[0:3] ports) and the latch on the
right-hand side.

2.1

Device Start-Up Modes

The LMK05318 can start-up in one of three modes depending on the 3-level input level sampled on the
HW_SW_CTRL pin upon power-on reset (POR). The start-up modes are listed in

Table 4

and determine

the following:

1. The memory bank (EEPROM or ROM) used to initialize the registers upon start-up.

2. The serial interface (I

C or SPI) used for register access.

3. The logic pin definitions.

The I

C or SPI interface allows for register access to configure the device after start-up and monitor its

status. The register map configurations are the same for I

C and SPI.

See

Section 3.2

for detailed descriptions of the logic pins for each start-up mode.

(1)

The input levels on these pins are sampled only during POR.

(2)

FINC and FDEC pin controls are only available when DCO mode and GPIO pin control are enabled by registers.

Table 4. Device Start-Up Modes

HW_SW_CTRL

(1)

INPUT LEVEL

START-UP MODE

MODE DESCRIPTION

(Soft pin mode)

Registers are initialized from EEPROM, and I

C interface is enabled with slave

address 11001xxb. Logic pins:

• SDA/SDI, SCL/SCK: I

C Data, I

C Clock

• GPIO0/SYNCN: Output Sync (active low)

• GPIO1/SCS

(1)

: I

C Address LSB Select (Low = 00b, Float = 01b, High = 10b)

• GPIO2/SDO/FINC

(2)

: DPLL DCO Frequency Increment (active high)

• STATUS1/FDEC

(2)

: DPLL DCO Frequency Decrement (active high), or Status

output

Float

)

SPI

(Soft pin mode)

Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:

• SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK)

• GPIO0/SYNCN: Output Sync (active low)

• GPIO1/SCS: SPI Chip Select (SCS)

• GPIO2/SDO/FINC: SPI Data Out (SDO)

ROM + I

(Hard pin mode)

Registers are initialized from the ROM page selected by GPIO pins, and I

C interface

is enabled with the 7-bit slave address of 0x64. Logic pins:

• SDA/SDI, SCL/SCK: I

C Data, I

C Clock

• GPIO[2:0]

(1)

: ROM page select at POR

• After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins can function the same

as for HW_SW_CTRL = 0 if enabled by registers.

TI suggests to use the EEPROM mode when either of the following is true:

•

A single custom start-up frequency configuration is required from a single OPN.

•

A host device is able to program the registers (and EEPROM, if needed) with a new configuration after
power-up through I

C or SPI. SPI is not supported by ROM mode.

Содержание LMK05318EVM

Страница 1: ...LMK05318EVM User s Guide Literature Number SNAU236A June 2018 Revised December 2018 ...

Страница 2: ... EVM Configuration 8 2 Device Under Test 10 2 1 Device Start Up Modes 10 3 EVM Configuration 11 3 1 Power Supply 13 3 2 Logic Inputs and Outputs 15 3 3 XO Input 18 3 4 Reference Clock Inputs 20 3 5 Clock Outputs 20 3 6 Status Outputs and LEDs 21 4 EVM Schematics 22 5 EVM Layouts 33 6 EVM Bill of Materials 45 Appendix A Software 51 A 1 Software Installation One Time 51 A 2 TICS Pro Usage for LMK053...

Страница 3: ...ic 3 DC DC Regulator 24 12 Schematic 4 LMK05318 and XO Input Interfaces 25 13 Schematic 5 Clock Input Interfaces 26 14 Schematic 6 Clock Output Interfaces OUT0 to OUT3 27 15 Schematic 7 Clock Outputs OUT4 to OUT7 28 16 Schematic 8 Logic I O Interfaces 29 17 Schematic 9 USB MCU and I2 C SPI Jumper Block 30 18 Schematic 10 LMK61E2 Oscillator 31 19 Schematic 11 DUT Test Socket 32 20 Top Composite Vie...

Страница 4: ...sion IDs 8 3 Default Configuration EEPROM Start Up Modes 9 4 Device Start Up Modes 10 5 Key EVM Components 11 6 Suggested DUT Power Configurations 14 7 Suggested XO Power Configurations 15 8 Logic Pin Mapping Tables 15 9 Logic Pin Descriptions EEPROM I2 C Mode HW_SW_CTRL 0 16 10 Logic Pin Descriptions EEPROM SPI Mode HW_SW_CTRL Float 17 11 Logic Pin Descriptions ROM I2 C Mode HW_SW_CTRL 1 18 12 Bi...

Страница 5: ...UI TICS Pro can be used to program the LMK05318 registers and on chip EEPROM which enables a custom clock configuration on power up Trademarks All trademarks are the property of their respective owners Features LMK05318 DUT DPLL with programmable loop bandwidth for input jitter and wander attenuation Two Analog PLLs APLLs for flexible low jitter clock generation Two clock inputs supporting hitless...

Страница 6: ...eded www ti com 6 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Introduction Figure 1 LMK05318EVM With Default Jumper and DIP Switch Settings ...

Страница 7: ...nected to MCU DUT Control Pins JP18 Tie pins 2 3 REFSEL 0 PRIREF selected if using Manual Pin mode JP19 Tie pins 2 3 HW_SW_CTRL 0 EEPROM I2 C Start up Mode selected S2 S2 1 3 OFF S2 4 ON STATUS0 Hi Z Output state shown on D7 Pin not connected to MCU S3 S3 1 3 OFF S3 4 ON STATUS1 FDEC Hi Z Output state shown on D8 Pin not connected to MCU S5 S5 1 ON S5 2 3 OFF GPIO0 SYNCN 1 SYNC deasserted Pin not ...

Страница 8: ... to program the LMK05318 through the USB interface a See Appendix A for TICS Pro installation and usage TICS Pro uses the USB2ANY API software driver to control the USB MCU interfaces I2 C SPI and Logic pins on the EVM TICS Pro can be used to access the device registers and program the device EEPROM for a different start up configuration 1 1 Device Revision Identification Pre production devices ma...

Страница 9: ...O1 0 I2 C Address 0x64h S6 1 OFF S6 2 3 ON SPI SCS input to MCU GPIO2 SDO FINC S7 Jumper Settings S7 1 OFF S7 2 3 ON Not used by default S7 1 OFF S7 2 3 ON SPI SDO output to MCU XO Input 48 0048 MHz DIFF or LVCMOS On chip termination disabled PRIREF and SECREF Clock Inputs 25 MHz DIFF or LVCMOS On chip termination disabled DPLL Clock Input Assignment PRIREF SECREF Highest to lowest priority order ...

Страница 10: ...OR 2 FINC and FDEC pin controls are only available when DCO mode and GPIO pin control are enabled by registers Table 4 Device Start Up Modes HW_SW_CTRL 1 INPUT LEVEL START UP MODE MODE DESCRIPTION 0 EEPROM I2 C Soft pin mode Registers are initialized from EEPROM and I2 C interface is enabled with slave address 11001xxb Logic pins SDA SDI SCL SCK I2 C Data I2 C Clock GPIO0 SYNCN Output Sync active ...

Страница 11: ...ange of LMK05318 use cases the EVM was designed with more flexibility and functionality than needed to implement the chip in a customer system application This section describes the power logic and clock input and output interfaces on the EVM as well as how to connect set up and operate the EVM An overview of some key components are shown in Table 5 Figure 2 and Figure 3 Table 5 Key EVM Components...

Страница 12: ...y Input 2B Terminal Main Supply Input 3B SMA Ports for External XO 3C Programmable XO 4 Reference Clock Inputs 5 Clock Outputs 6 PDN switch 7 Jumper for DPLL input sel 8 Status LEDS 9 I2C SPI Jumpers 10 USB port EVM Configuration www ti com 12 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 2 Key C...

Страница 13: ...e 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 3 Key Components EVM Bottom Side 3 1 Power Supply The LMK05318 has five core VDD supply pins that operate from 3 3 V 5 and six output VDDO supply pins that operate from 1 8 V 2 5 V or 3 3 V 5 J1 is the main power terminal to the external power supply Power SMA po...

Страница 14: ...ns and settings Figure 4 Default Power Jumper Configuration Table 6 shows the suggested power configurations for the DUT 1 The SMA ports J2 or J3 can be used to power VIN1 or VIN2 respectively through a coaxial cable instead of using power cables to J1 Table 6 Suggested DUT Power Configurations CONNECTION NAME ONBOARD LDO REGULATORS DEFAULT DIRECT EXTERNAL SUPPLIES VDD 3 3 V LDO1 VDDO 1 8 2 5 3 3 ...

Страница 15: ...t the power and signal paths from any XO circuit that is not used for a given configuration to avoid unwanted noise coupling 3 2 Logic Inputs and Outputs The logic I O pins of the DUT support different functions depending on the device start up mode chosen by the HW_SW_CTRL input level upon POR The STATUS 0 1 pins are programmable and can be used to monitor a variety of different device statuses T...

Страница 16: ...PIO0 SYNCN can be used to mute the output clocks and trigger output divider synchronization SYNC if the divider SYNC bits are enabled by registers Alternatively SYNC can be triggered through register programming instead of using this pin This pin is set through a 3 position DIP switch S5 When S5 2 ON default the pin is connected to the MCU and can be driven 0 or 1 by software control When S5 2 OFF...

Страница 17: ...llup or pulldown switch determines the state FDEC STATE S3 0 OFF 1 ON DPLL DCO NUMERATOR 0 S3 1 3 X1X MCU driven No update 1 Pulsed by MCU pin Decremented 1 Logic pins not listed in Table 10 are the same as described in Table 9 2 When HW_SW_CTRL Float STATUS 1 0 pins must not be pulled high or low externally during POR to ensure proper start up into EEPROM SPI Mode Table 10 Logic Pin Descriptions ...

Страница 18: ...ATUS1 FDEC description in Table 9 3 3 XO Input The LMK05318 has an XO input XO_P N pins to accept a reference clock for the Fractional N APLLs The XO input determines the output frequency accuracy and stability in free run or holdover modes For synchronization applications like SyncE or IEEE 1588 the XO input would typically be driven by a low frequency TCXO OCXO or external traceable clock that c...

Страница 19: ...powered down by JP21 Tie pins 2 3 Figure 5 XO Input Interface 1 of 2 48 0048 MHz Oscillator and SMA Ports 3 3 3 LMK61E2 Programmable Oscillator The last option is to use the other onboard LMK61E2 programmable oscillator U10 to drive the XO_P N inputs See Figure 6 The differential output clock from U10 can be routed to the XO_P N input pins with minimal rework by placing 0 1 µF capacitors on C137 a...

Страница 20: ...d store the new configuration to the LMK61E2 s internal EEPROM if desired After U10 has been programmed set S9 1 2 to the OFF positions to disconnect it from the I2 C bus Figure 6 XO Input Interface 2 of 2 LMK61E2 Oscillator 3 4 Reference Clock Inputs The LMK05318 has two DPLL reference clock input pairs PRIREF_P N and SECREF_P N with configurable input priority and input selection modes The input...

Страница 21: ...SL output clocks Each output pair supports AC LVDS CML LVPECL and HCSL driver types The HCSL driver has programmable on chip termination or can used external termination OUT 4 7 can also support 1 8 V LVCMOS driver type with one or two LVCMOS output clocks per P N pair Each LVCMOS driver has internal 50 Ω output impedance and supports programmable polarity and tri state options Figure 8 Clock Outp...

Страница 22: ...ics www ti com 22 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide 4 EVM Schematics Figure 9 Schematic 1 Power Supplies ...

Страница 23: ...i com EVM Schematics 23 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 10 Schematic 2 Power Distribution ...

Страница 24: ... Schematics www ti com 24 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 11 Schematic 3 DC DC Regulator ...

Страница 25: ...VM Schematics 25 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 12 Schematic 4 LMK05318 and XO Input Interfaces ...

Страница 26: ...ematics www ti com 26 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 13 Schematic 5 Clock Input Interfaces ...

Страница 27: ... Schematics 27 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 14 Schematic 6 Clock Output Interfaces OUT0 to OUT3 ...

Страница 28: ...atics www ti com 28 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 15 Schematic 7 Clock Outputs OUT4 to OUT7 ...

Страница 29: ... com EVM Schematics 29 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 16 Schematic 8 Logic I O Interfaces ...

Страница 30: ...cs www ti com 30 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 17 Schematic 9 USB MCU and I2 C SPI Jumper Block ...

Страница 31: ...i com EVM Schematics 31 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 18 Schematic 10 LMK61E2 Oscillator ...

Страница 32: ...Schematics www ti com 32 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 19 Schematic 11 DUT Test Socket ...

Страница 33: ...ti com EVM Layouts 33 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide 5 EVM Layouts Figure 20 Top Composite View ...

Страница 34: ...EVM Layouts www ti com 34 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 21 Top Solder Mask ...

Страница 35: ...ts 35 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 22 Layer 1 Top Side Clock I Os Logic and Power Routing Ground Fill ...

Страница 36: ...EVM Layouts www ti com 36 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 23 Layer 2 Ground Plane ...

Страница 37: ...i com EVM Layouts 37 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 24 Layer 3 Logic Routing Ground Fill ...

Страница 38: ...ayouts www ti com 38 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 25 Layer 4 Power Routing Ground Fill ...

Страница 39: ...ti com EVM Layouts 39 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 26 Layer 5 Power and Ground Planes ...

Страница 40: ...ayouts www ti com 40 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 27 Layer 6 Logic Routing Ground Fill ...

Страница 41: ...www ti com EVM Layouts 41 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 28 Layer 7 Ground Plane ...

Страница 42: ...42 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 29 Layer 8 Bottom Side View From Top Logic and Power Routing Ground Fill ...

Страница 43: ...www ti com EVM Layouts 43 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 30 Bottom Solder Mask ...

Страница 44: ...EVM Layouts www ti com 44 SNAU236A June 2018 Revised December 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMK05318EVM User s Guide Figure 31 Bottom Composite View ...

Страница 45: ...8 C39 C40 C41 C48 C49 C50 C51 C52 C53 C54 C68 C69 C70 C73 C78 C85 C126 C129 C135 27 10uF CAP CERM 10 uF 10 V 20 X5R 0603 C1608X5R1A106M080AC TDK C20 C26 C27 C28 C29 C133 6 0 01uF CAP CERM 0 01 uF 50 V 5 X7R 0603 C0603C103J5RACTU Kemet C21 C22 C32 C33 C34 C35 C36 C42 C43 C44 C45 C46 C47 C56 C76 C80 C83 C84 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C108 C109 C110 C134 C136 R34 R35 ...

Страница 46: ... C124 2 220pF CAP CERM 220 pF 50 V 1 C0G NP0 0603 06035A221FAT2A AVX C121 C150 2 0 47uF CAP CERM 0 47 uF 10 V 10 X7R 0603 GRM188R71A474KA61D MuRata C128 1 2200pF CAP CERM 2200 pF 50 V 10 X7R 0603 C0603C222K5RACTU Kemet C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 11 1uF CAP CERM 1 uF 6 3 V 20 X5R 0402 GRM152R60J105ME15D MuRata C152 C154 2 10uF CAP CERM 10 uF 16 V 10 X5R 0805 GRM21BR61C10...

Страница 47: ...T 1734035 2 TE Connectivity JP1 JP2 JP3 JP16 JP17 JP18 JP19 JP21 JP22 JP23 10 Header 100mil 3x1 Gold TH TSW 103 07 G S Samtec JP4 1 Header 100mil 3x2 Gold TH TSW 103 07 G D Samtec JP20 1 Header 100mil 7x2 Tin TH PEC07DAAN Sullins Connector Solutions JT1 JT2 JT3 JT4 JT5 5 Header 100mil 1pos Gold TH TSW 101 07 G S Samtec L1 L2 2 2 2uH Inductor Multilayer Ferrite 2 2 uH 1 3 A 0 08 ohm SMD LQM2HPN2R2M...

Страница 48: ...603 CRCW06031K00JNEA Vishay Dale R149 R158 R183 3 100 RES 100 5 0 1 W AEC Q200 Grade 0 0603 CRCW0603100RJNEA Vishay Dale R167 R176 R186 3 33k RES 33 k 5 0 1 W AEC Q200 Grade 0 0603 CRCW060333K0JNEA Vishay Dale R168 R169 2 33 RES 33 5 0 063 W AEC Q200 Grade 0 0402 CRCW040233R0JNED Vishay Dale R170 1 1 5k RES 1 5 k 5 0 063 W AEC Q200 Grade 0 0402 CRCW04021K50JNED Vishay Dale R171 1 1 2Meg RES 1 2 M ...

Страница 49: ... Synchronizer and Jitter Cleaner with Two Frequency Domains Eight Differential Outputs Two Differential Inputs RGZ0048N VQFN 48 LMK05318RGZR Texas Instruments U6 1 4 Channel ESD Protection Array for High Speed Data Interfaces DRY0006A USON 6 TPD4E004DRYR Texas Instruments U7 1 25 MHz Mixed Signal Microcontroller with 128 KB Flash 8192 B SRAM and 63 GPIOs 40 to 85 degC 80 pin QFP PN Green RoHS and ...

Страница 50: ...R50 R51 R52 R53 R64 R65 R66 R67 R74 R75 R76 R77 R82 R83 R84 R85 R92 R93 R94 R95 R100 R101 R102 R103 R110 R111 R112 R113 R118 R119 R120 R121 R128 R129 R130 R131 0 49 9 RES 49 9 1 0 1 W AEC Q200 Grade 0 0603 CRCW060349R9FKEA Vishay Dale R54 R55 0 100 RES 100 1 0 1 W AEC Q200 Grade 0 0603 CRCW0603100RFKEA Vishay Dale R68 R70 R71 R73 R86 R88 R89 R91 R104 R106 R107 R109 R122 R124 R125 R127 0 0 RES 0 5 ...

Страница 51: ...P20 jumpers accordingly for I2 C or SPI Mode ii Click Yes to confirm change or No to cancel d Press Close to apply the Mode Protocol changes 6 Follow the dialogs a Scan I2 C Bus Yes to confirm No to skip LMK05318 should be found at 0x64 0x65 or 0x66 depending on the GPIO1 SCS input level set by S6 or MCU control If the scan found a device at 0x58 it is probably U7 LMK61E2 In this case restart from...

Страница 52: ... setting descriptions in the Default Jumper and DIP Switch Settings table 7 Added Device Revision Identification section 8 Updated the Default Configuration EEPROM Start Up Modes table 9 Added design suggestions whille using EEPROM mode in the Device Start Up Modes section 10 Updated the Key EVM Components table 11 Updated the Logic Pin Mapping tables 15 Updated the Bill of Materials table 45 Remo...

Страница 53: ...y set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warr...

Страница 54: ...the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la réglementation d Industrie Canada le présent émetteur radio peut fo...

Страница 55: ...ed loads Any loads applied outside of the specified output range may also result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Please consult the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even ...

Страница 56: ...COST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE 12 MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED 8 2 Specif...

Страница 57: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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