Recommended Test Equipment
13
SNAU252 – June 2020
Copyright © 2020, Texas Instruments Incorporated
LMK04832EVM-CVAL User’s Guide
Table 5. Description of Evaluation Board Inputs and Outputs (continued)
CONNECTOR NAME
SIGNAL TYPE,
INPUT/OUTPUT
DESCRIPTION
SPI Header
USB2ANY (J43)
SDIO (TP17),SCK
(TP14),CS* (TP19)
CLKin_SEL0(TP10),CL
Kin_SEL1(TP11)
RESET(TP13)
CMOS,
Input/Output
10-pin header for SPI programming interface and programmable logic I/O pins for
the LMK04832-SP.
SPI signals include SDIO (TP17), SCK (TP14) and CS* (TP19).
The programmable logic I/O signals accessible through this header include: RESET
(TP13), SYNC (TP20/J44), CLKin_SEL0 (TP10), and CLKin_SEL1 (TP11).
Input Clock Switching – Pin Select Mode
By default CLKin_SEL0 and CLKin_SEL1 are input pins. To enable input clock
switching, CLKin_SEL_AUTO_EN = 0, CLKin_SEL_PIN_EN = 1,
CLKin_SEL_PIN_POL = 0, and Status_CLKinX_TYPE must be 0 to 3 (pin enabled
as an input).
When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 1, the Status_CLKinX
pins select which clock input is active as follows:
CLKin_SEL1
CLKin_SEL0
Active Clock
0
0
CLKin0
0
1
CLKin1
1
0
CLKin2
1
1
Holdover
SYNC
SYNC (TP20/J44)
CMOS,
Input/Output
Programmable status I/O pin. By default, set as an input pin for synchronize the
clock outputs with a fixed and known phase relationship between each clock output
selected for SYNC. A SYNC event also causes the digital delay values to take
effect.
SYNC/SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous mode
(0x03) when SYSREF_REQ_EN = 1.
SYNC/SYSREF_REQ pin can hold outputs in a low state, depending on system
configuration. SYNC_POL adjusts for active low or active high control.
A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the
SYNC/SYSREF
page
in TICS Pro.
Status LEDs
Status_LD1(TP18),Stat
us_LD2(TP21)
CMOS,
Input/Output
Programmable status output pin. By default, Status_LD1 and Status_LD2 are set to
output the digital lock detect status signal for PLL1 and the digital lock detect status
signal for PLL2 respectively.
By default TICS Pro configuration, LEDs will illuminate green when lock is detected
(output is high) and turned off when lock is lost (output is low).
7
Recommended Test Equipment
Power Supply
The Power Supply must be a low-noise power supply, particularly when the devices on the board are
being directly powered (onboard LDO regulators bypassed).
Phase Noise / Spectrum Analyzer
TI recommends that an Agilent E5052 Signal Source Analyzer or comparable test equipment is used to
measure phase noise and RMS jitter.
Oscilloscope
To measure the output clocks AC performance, such as rise time or fall time, propagation delay, or skew,
TI suggests using a real-time oscilloscope with 8+ GHz analog input bandwidth with 50-
Ω
inputs. To
evaluate clock synchronization or phase alignment between multiple clock outputs, TI recommends using
phase-matched, 50-
Ω
cables to minimize external sources of skew or other errors/distortion that may be
introduced if using oscilloscope probes.
8
Length Matching
Specific traces on the LMK04832EVM-CVAL were length matched to ensure device functions such as
skew and 0-delay mode phase could be tested.
contains the lengths of each of the traces on the
EVM.
