3.3-V LVCMOS
Driver
Ro = 50
LMK03328
375
SECREF_P
125
Configuring the EVM
4.4
Configuring the Reference Inputs
The LMK03328 has two reference input pairs, PRIREF and SECREF, which can be configured to accept
single-ended clock input, differential clock input, or crystal input (SECREF only). The input SMAs labeled
PRI_P and PRI_N are routed to the PRIREF inputs, and SMAs labeled SEC_P and SEC_N are routed to
the SECREF inputs. Both SMA input pairs are routed using 50-ohm single-ended traces to the input pins
of the chip.
The PRI_P and PRI_N input SMAs are DC-coupled on the EVM and have no on-board terminations at the
PRIREF input pins (high impedance inputs). By default, a LVCMOS clock input with 1.5V to 3.3V levels
can be connected to the PRI_P input for DC-coupling to the PRIREF_P input (assumes the LVCMOS
driver is source-terminated). The unused complementary input (PRIREF_N) can be tied to GND. If a
differential clock source is required, LMK03328 supports programmable input termination and common-
mode biasing options (through 200 kohm internal bias resistors) for either DC- or AC-coupled inputs.
The SECREF input pins of the LMK03328 can accept a fundamental-mode crystal for the internal crystal
oscillator circuit. By default, R40 and R41 are installed to enable the onboard 50-MHz crystal (Y1), which
can be selected as the PLL reference input when using the Soft Pin Mode configurations listed in
.
If a different crystal is required for the intended configuration (e.g. Register Default or Hard Pin mode
configurations), remove the original crystal on Y1 and install the new part. The new part should comply
with the recommended crystal characteristics specified in the LMK03328 datasheet. If using a crystal with
high load capacitance spec (e.g. 18 pF), external trim capacitors may be installed on C58 and C59 to
supplement the on-chip load capacitance.
The SECREF_P and SECREF_N input SMAs are AC-coupled on the EVM and have 100-ohm center-
tapped differential termination near the inputs. The input common-mode voltage is biased to 1.2 V when
tying pins 1-2 on JP16. If using a differential clock input to SEC_P and SEC_N, remove R40 and R41 to
disconnect the crystal input path and install 0 ohms on R36 and R37. If using a LVCMOS clock input with
1.5V to 2.5V levels to SEC_P, remove R40 and R41 to isconnect the crystal path, install 0 ohms on C51
and C52, and remove R33 and R34 to provide a DC-coupled, high-impedance path to the SECREF_P
input (assumes the LVCMOS driver is source-terminated). The unused complementary input (SECREF_N)
can be tied to GND. If using a 3.3-V LVCMOS clock input to SECREF_P, a voltage divider network is
required, like shown in
, to comply with the maximum single-ended input swing of 2.6 V. The
resistive divider can be installed on R29 and R33 with the shunt resistor connected to GND by tying pins
2-3 of JP16.
Figure 5. Interfacing a 3.3-V LVCMOS Clock Input to SECREF_P
16
LMK03328EVM User’s Guide
SNAU184 – August 2015
Copyright © 2015, Texas Instruments Incorporated
