Texas Instruments FlatLink SN75LVDS83B, Руководство пользователя

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CLKSEL
DUT_GND
SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V
1p2V 3p3V
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V 3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
U1
PIN 1
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
LVDS
Timing
Controller
(6bpc, 18bpp)
Notes:
Current setup uses rising edge triggered clocking. If rising edge triggered
clocking is desired, place jumper to create LOW level input at JMP7.
Leave output Y3 NC (No Connection).
*R3, G3, and B3 are MSB that may be connected to the 5
th
bit of each color
increased dynamics range of entire color space at the expense of non-
linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
*R32 G2, and B2 may be connected to the LSB of each color increased
dynamics range of entire color space at the expense of non-linear step
sizes between each step. For linear steps with less dynamic range,
connect D0, D7, and D15 to VCC.
100
Pa
n
e
l C
o
n
n
e
ct
o
r
Ma
in
Bo
a
rd
C
o
n
n
e
ct
o
r
100
100
100
12-bpc GPU
R2 or Vcc*
R3 or GND*
R0 (LSB)
R1
R2
R3 (MSB)
G2 or Vcc*
G3 or GND*
G0 (LSB)
G1
G2
G3 (MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B2 or Vcc*
B3 or GND*
B0 (LSB)
B1
B2
B3 (MSB)
24bpp LCD Display
F
PC
C
a
b
le
To Column Driver
To Row Driver
CLKIN
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23 S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
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LVDS83BTSSOPEVM Configuration
9 SNLU233 – October 2017
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LVDS83BTSSOPEVM User’s Guide
Figure 8. 12-Bit Color Host to 18-Bit LCD Panel Application