CLKIN
CLKSEL
DUT_GND
SHTDN
DUT_GND
Power Supply
GND
1p8V
2p5V
3p3V
1p2V
3p3V
VCCIO
DUT_GND SIGNAL_GND
VCC
1p8V
2p5V
3p3V
3p3V
P1
P2
P3
P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN 1
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
24bpp LCD Display
F
PC
C
a
b
le
LVDS
Timing
Controller
(8bpc, 24bpp)
Notes:
Current setup uses rising edge triggered clocking. If
rising edge triggered clocking is desired, place jumper
to create LOW level input at JMP7.
100
To Column Driver
Pa
n
e
l C
o
n
n
e
ct
o
r
Ma
in
Bo
a
rd
C
o
n
n
e
ct
o
r
100
100
100
100
To Row Driver
24-bpc GPU
R0 (LSB)
R1
R2
R3
R4
R5
R6
R7 (MSB)
G0 (LSB)
G1
G2
G3
G4
G5
G6
G7 (MSB)
HSYNC
VSYNC
ENABLE
RSVD
CLK
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7 (MSB)
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
LVDS83BTSSOPEVM Configuration
6
SNLU233 – October 2017
Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
This configuration is most popular for 24-bit panels.
Figure 5. 24-Bit Color Host to 24-Bit LCD Panel Application
With 2 MSB Transfer Over Fourth Data Channel
