Texas Instruments FlatLink SN75LVDS83B, Руководство пользователя

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CLKIN
CLKSEL
DUT_GND SHTDN
DUT_GND
VCCIO DUT_GND SIGNAL_GND VCC
1p8V
2p5V
3p3V
3p3V
P1 P2 P3 P4
LVDS83BTSSOPEVM
INT061A
SIGNAL_GND
DUT_GND
Y2M
J6
Y0P
J9
Y1M
J8
J7
JMP6
U1
PIN 1
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
JMP4
JMP3
JMP2
JMP1
D0
D1
D2
D3
D4
D6
D7
D27
D5
D10
D11
D16
D17
D23 S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
S
IG
N
A
L
_
G
N
D
JMP7
JMP8
Y0M
J10
Y2P
J5
CLKINM
J2
Y3M
J4
Y3P
J3
CLKINP
J1
Y1P
C1
C3
C4
C5
C10
C9
C8
C7
C6
C11
C12
C13
C14
C15
C2
R2
R1
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Introduction
3 SNLU233 – October 2017
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Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
1 Introduction
The SN75LVDS83B FlatLink transmitter is a single integrated circuit which contains four 7-bit, parallel-
load, serial-out, shift registers, a 7x clock synthesizer, and LVDS line drivers. This user’s guide describes
the construction and handling of the EVM for the SN75LVDS83B. The guide serves as an evaluation tool
for the SN75LVDS83B, as well as a reference design for the device.
Figure 1. LVDS83BTSSOPEVM
2 LVDS83BTSSOPEVM Configuration
2.1 LVDS83BTSSOPEVM Kit Contents
This EVM kit contains the following items:
• LVDS83BTSSOPEVM board
• LVDS83BTSSOPEVM User’s Guide
2.2 Description of EVM Board
The LVDS83BTSSOPEVM is designed to provide straightforward evaluation of the SN75LVDS83B device
using four 7-bit, parallel-load, serial-out, shift registers. Power to the board is provided through banana
jacks P4 for VCC and P1 for VCCIO. For correct board operation, power must be fixed at VCC = 3.3 V,
and the I/O power (VCCIO) may be adjusted at 1.8 V, 2.5 V, or 3.3 V.
The transmission of data bits D0 through D27 occurs as each bit is loaded into registers upon the edge of
the CLKIN signal (JMP5), where the rising or falling edge of the clock may be selected using CLKSEL
(JMP7). To select a clock rising edge, input a high level to CLKSEL. Removing the strap on the jumper
allows the pull-up resistor to pull CLKSEL=high (see
Figure 2 ). To input a low level to select a clock falling
edge, place the strap on the jumper to allow a path to GND (see Figure 3 ).
Additionally, use of SHTDN (JMP8) for possible Shutdown/Clear settings can be obtained with an active-
low input, by placing the strap on the jumper to allow a path to GND, which inhibits the clock and shuts off
the LVDS output drivers for lower power consumption (see
Figure 4 ). A low-level on this signal clears all
internal registers to a low-level. Remove the strap on JMP8 to enable the device for normal operation.