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during micromirror reset, which improves system contrast. For the system timing specifications of the
DLP3021LEQ1EVM, see
Figure 1-6 .
Figure 1-6. LED Driver Timing Specifications
The timing specifications are shown in Table 1-5 .
Table 1-5. LED Driver Timing Specifications
PARAMETER VALUE
T
r1
, T
f2
< 50 μs
T
f1
, T
r2
< 2 μs
T
w
minimum = 1 μs
1.3.4 Video Specification
In this architecture, video content is compressed and stored in external flash memory. Low speed SPI
commands are sent from the MSP430 MCU in Local Host Control operating mode or FTDI interface in Host
Mute operating mode to the DMD controller to indicate what image/video content to read from the external 2Gb
flash memory. Storing the image/video content in memory removes the need for a high-speed video interface
to the module which improves compatibility with typical vehicle infrastructures. It also decreases overall system
size and cost by removing graphics generation and interfaces. The controller decompresses each bit plane of
the video data (608 × 684 resolution) and displays them on the DMD in rapid succession to create the full video
image at a frame rate of 25 Hz. A frame rate of 25 Hz is recommended due to memory constraints, but the
DLP3021-Q1 can support a maximum frame rate of 60 Hz. Due to the diamond format of the DMD pixels, the
output image has an effective resolution of 864 × 480. The controller synchronizes the DMD bit plane data with
the RGB enable timing for the LED color controller and driver circuit.
www.ti.com DLP3021-Q1 Electronics EVM Overview
DLPU106A – MARCH 2021 – REVISED OCTOBER 2021
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DLP3021LEQ1EVM Evaluation Module 9
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