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videos within flash so that they can be loaded dynamically by an MCU, such as the MSP430G2553-Q1 on the
EVM. The flash information block is divided into four main sections as shown in
Table 4-2 . Information such as
the number of sequences is provided so that software can navigate the flash block and determine the correct
offset for the data of interest. The number of sequence and video entries in the information block is variable, but
each entry is a fixed size.
Table 4-2. Flash Information Block
Offset (HEX) 0 1 2 3
00 Major Minor Patch
04 “D” “E” “F” “C”
08 Block Address
0C Count (Number of Register Writes)
10 “S” “E” “Q” “L”
14 Size (of Sequence Block)
18 Count (Number of Sequences)
1C Sequence 0 Address
20 Seq 0 Red Duty Cycle Seq 0 Green Duty Cycle
24 Seq 0 Blue Duty Cycle Seq 0 Frame Rate
28 Sequence 1 Address
2C Seq 1 Red Duty Cycle Seq 1 Red Duty Cycle
30 Seq 1 Blue Duty Cycle Seq 1 Blue Duty Cycle
34 Sequence … Address
38 Seq … Red Duty Cycle Seq … Red Duty Cycle
3C Seq … Blue Duty Cycle Seq … Blue Duty Cycle
Variable “V” “I” “D” “E”
Variable Size (of Video Block)
Variable Count (Number of Videos)
Variable Video 0 Address
Variable Video 0 Frame Rate Video 0 Frame Count
Variable Video 1 Address
Variable Video 1 Frame Rate Video 1 Frame Rate
Variable Video … Address
Variable Video … Frame Rate Video … Frame Rate
Sequences
Sequences are generated by DLP Composer based on the duty cycle selection. Each sequence entry is
reserved 4kB in flash.
Videos
Videos and still image content are an input to a dynamic ground projection project in DLP Composer. Composer
takes the content, scales it, converts it to a sequence of DMD native format bit-planes, and compresses it
using run length encoding (RLE) for storage in flash. When a video or still image is to be shown, the FPGA
decompresses each bit-plane and displays in the order and with the timings specified by the sequence.
Default Configuration
The default configuration block is the set of values for each of the FPGA registers. This information is loaded by
the FPGA after the completion of the FPGA configuration. These values supersede the power-on default values
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20 DLP3021LEQ1EVM Evaluation Module DLPU106A – MARCH 2021 – REVISED OCTOBER 2021
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