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Parallel Control
4.9 SN74LVC139 Outputs
Table 6 through Table 8 show the truth tables for the outputs of the SN74LVC139. Note that A3 to A0
correspond to the signals from the J1 header.
Table 6. A0 and A1 Address Combinations
A1 A0 RST CLR R/W LATCH_CTRL
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1
Table 7. A2 and A3 Address Combinations
A3 A2 LDAC DC_CS2 DC_CS1 DC_CS0
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1
Table 8. Commonly-Used Address Combinations
A3 to A0 (Hex)
Open1 + LATCH_CTRL 0x0
DC_CS + R/W 0x5
LDAC + LATCH_CTRL 0xC
DC_CS + Open2 0x7
4.10 BUSY Signal
The BUSY signal is routed to an interrupt on the host processor; this allows the user to monitor the state
of the correction engine. The BUSY pin is pulled low when the correction engine runs, and is pulled high
by an external pull-up when the correction process completes.
9 SBAU161 – February 2010 DAC8728EVM
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