Texas Instruments DAC8728EVM Скачать руководство пользователя страница 12

Reference Voltage

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6

Reference Voltage

The DAC8728EVM is configured with two different onboard precision references. The evaluation module
has both a +2.5V and +5V reference using the REF5025 and the REF02, respectively. By using the screw
terminal J2, the user can also apply external reference voltages to the board. Any external voltage applied
to J2 must be within the +1.0 to +5.5V reference voltage range specification for the DAC8728. The
DAC8728 has two different references, REF_A for V

OUT

0–V

OUT

3 and REF_B for V

OUT

4–V

OUT

7, respectively.

Using jumpers JP4 to JP7, both REF_A and REF_B can be individually configured to 2.5V, +5V, or
the external reference input voltage. Jumpers JP6 (REF-A) and JP7 (REF-B) are used to select between
using an onboard reference or an external reference. If an onboard reference is selected, jumpers JP4
(REF-A) and JP5 (REF-B) are used to select between the 2.5V or the 5.0V reference. The reference
circuits can be seen in the schematic at the end of this document.

7

EVM Operation

CAUTION

Before power is applied to J4 on the EVM, be sure that the jumpers on the
board are configured according to the factory default settings described below.

This section provides information on the analog input and digital control of the DAC8728EVM, as well as
the default settings.

7.1

Analog Output

The DAC8728 has eight analog outputs that are available at the J5 header or the JP1 and JP2 jumper
headers. Each of these outputs is referenced to the board ground.

Jumpers JP1 and JP2 allow the user to route the DAC outputs to the input of a voltage-follower amplifier
that drives an RC low-pass filter. The capacitor is not installed and a 0

Ω

resistor connects the op amp

output to the test-points. A filter can be installed by replacing the 0

Ω

resistor and installing a capacitor.

CAUTION

Only one shunt may be placed across each header. If more than one shunt is
placed across either JP1 or JP2, it will directly short two of the DAC analog
outputs together, possibly causing irreversible damage to the DAC8728.

The OFFSET-A and OFFSET-B analog outputs are routed to TP10 and TP17. The OFFSET feature can
only be used in bipolar mode. In unipolar mode, a shunt must be placed across JP8 and JP16 to connect
the OFFSET-x pins to the board ground.

V

MON

is the channel monitor output. It can relay any of the eight analog output signals, the OFFSET-A/B,

and the Ref Buffer A/B. The output pin has a 0.1

m

F capacitor connected. By default, the V

MON

pin is in

3-state mode.

7.2

Digital Control

The digital control signals can be applied directly to J1 (top or bottom side). The DAC8728EVM can also
be connected directly to a DSP or microcontroller interface board.

No specific evaluation software is provided with this EVM; however, various code examples are available
that show how to use this EVM with a variety of digital signal processors from Texas Instruments. Check
the specific device product folders on the

TI web site

or send an e-mail to

[email protected]

for a

listing of available code examples. The EVM Gerber files are also available on request.

12

DAC8728EVM

SBAU161 – February 2010

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Copyright © 2010, Texas Instruments Incorporated

Содержание DAC8728EVM

Страница 1: ...e circuit descriptions schematic diagrams and bills of material are included in this document The following related documents are available through the Texas Instruments web site at www ti com Related...

Страница 2: ...pply Configuration 15 List of Tables 1 J5 Analog Output Connector Pinout 3 2 J2 Parallel Interface Pins 5 3 External Logic Behavior 6 4 SN74LVC374 Control 7 5 LDAC Control 7 6 A0 and A1 Address Combin...

Страница 3: ...ety of processors Consequently access to the parallel interface is achieved through external logic controlled by the host processor parallel interface Throughout this document the acronym EVM and the...

Страница 4: ...r line decoder demultiplexer U7 on EVM This device is used to create eight control bits from the processor address that are used around the board to control various signals such as the LATCH input to...

Страница 5: ...mpletes DSP Write Strobe Signal is cycled low to J2 3 WE high within the CE strobe when a parallel bus write occurs DSP Read Strobe Signal is cycled low to J2 5 RE high within the CE strobe when a par...

Страница 6: ...nections to the SN74LVC139 Figure 1 Parallel Control Header and SN74LVC139 4 1 Required External Logic Most of TI s host processors do not have a hardware chip select that meets the timing requirement...

Страница 7: ...374 Control LATCH_CTRL WE LATCH 0 0 0 0 1 1 1 0 1 1 1 1 The final piece of external logic gives the EVM user the ability to control the LDAC signal from both the processor I O pins and the SN74LVC139...

Страница 8: ...on the 1Y0 output of the SN74LVC139 U7 The LATCH_CTRL signal is logic ORed with the WE signal to create the LATCH signal that is used to control the CLK input to the SN74LVC374 on the EVM During the...

Страница 9: ..._CS0 0 0 1 1 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 Table 8 Commonly Used Address Combinations A3 to A0 Hex Open1 LATCH_CTRL 0x0 DC_CS R W 0x5 LDAC LATCH_CTRL 0xC DC_CS Open2 0x7 4 10 BUSY Signal The...

Страница 10: ...d TSM 116 01 T DV to provide a convenient 16 pin dual row header socket combination at J6 This header socket combination provides access to the parallel data pins of the DAC8728 and the inputs to the...

Страница 11: ...ed from VA a 8 to 36V analog supply range When the DAC8728 is run in bipolar mode AVSS and AVDD are required AVSS can range from 4 5V to 18V and AVDD can range from 4 5V to 18V The DAC8728 AVDD VA sup...

Страница 12: ...pers JP1 and JP2 allow the user to route the DAC outputs to the input of a voltage follower amplifier that drives an RC low pass filter The capacitor is not installed and a 0 resistor connects the op...

Страница 13: ...ht binary Sets the DAC8728 to unipolar operation by routing JP14 2 3 the AVSS pin to AGND Sets the DVDD input to the DAC8728 to 3 3V from JP15 1 2 pin 10 on the J4 header Routes the OFFSET_B pin direc...

Страница 14: ...ET_B pins must be shorted directly to GND for unipolar single supply operation Table 11 Unipolar Single Supply Configuration Jumper Position JP3 JP4 JP5 JP6 JP7 JP9 1 2 JP15 JP17 JP19 JP20 JP14 2 3 JP...

Страница 15: ...dual supply operation Table 12 Bipolar Dual Supply Configuration Jumper Position JP3 JP4 JP5 JP6 JP7 JP9 1 2 JP14 JP15 JP17 JP19 JP20 JP1 JP2 JP8 JP13 JP16 JP18 Open JP11 Closed JP10 3 4 Figure 6 Bip...

Страница 16: ...r Ceramic 10mF 50V X7S 1210 Taiyo Yuden UMK325C7106MM T C27 11 3 J1 J3 J5 Top 20 pin header Samtec TSM 110 01 T DV 12 3 J1 J3 J5 Bottom 20 pin socket Samtec SSW 110 22 S D VS 13 1 J2 TERMINAL BLOCK 3...

Страница 17: ...Op Amp 8 SOP TI OPA227UA 35 1 U4 Dual Precision Op Amp 8 SOP TI OPA2277U 36 2 U5 U6 Little Logic OR Gate SOT23 5 TI SN74LVC1G32DBV 37 1 U7 Dual 2 4 Line Decoder 16 SOP TI SN74LVC139AD 38 2 U8 U12 Litt...

Страница 18: ...4 2B3 16 2B4 17 2B5 19 2B6 20 2B7 22 2B8 23 1A1 47 1A2 46 1A3 44 1A4 43 1A5 41 1A6 40 1A7 38 1A8 37 2A1 36 2A2 35 2A3 33 2A4 32 2A5 30 2A6 29 2A7 27 2A8 26 U10 SN74LVC16245A IOVDD R8 15k IOVDD EVM_A0...

Страница 19: ...oduct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engine...

Страница 20: ...h statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury...

Страница 21: ...ltera Analog Devices Intersil Interpoint Microsemi Aeroflex Peregrine Syfer Eurofarad Texas Instrument Miteq Cobham E2V MA COM Hittite Mini Circuits General Dynamics 8 812 309 58 32 8 812 320 02 42 or...

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