Texas Instruments DAC8728EVM, Руководство пользователя, Страница: 13 / 21

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EVM Operation
7.3 Default Jumper Settings and Switch Positions
The default configuration of the DAC8728EVM is summarized in Table 10 .
Table 10. DAC8718EVM Factory Default Configuration
Reference Jumper-position (s) Function
Can be used to route any of the V
OUT
-0 to V
OUT
-3
JP1 Open signals to the input of the OPA2277 to be low-pass
filtered and buffered
Can be used to route any of the V
OUT
-4 to V
OUT
-7
JP2 Open signals to the input of the OPA2277 to be low-pass
filtered and buffered
CLR is controlled by the 1Y2 output of the
JP3 1-2
SN74LVC139
The REF2.5V output of the REF5025 is routed to
JP4 1-2
JP6
The REF2.5V output of the REF5025 is routed to
JP5 1-2
JP7
The output of the JP4 jumper (REF2.5V Default) is
JP6 1-2
routed to the REF_A input of the DAC8728
The output of the JP5 jumper (REF2.5V Default) is
JP7 1-2
routed to the REF_B input of the DAC8728
Routes the OFFSET_A pin directly to AGND which
JP8 Closed
is required for single-supply operation
RST is controlled by the 1Y3 output of the
JP9 1-2
SN74LVC139
DC_CS is set to the 2Y1 output of the
JP10 3-4 SN74LVC139 which is controlled with the A2 and
A3 address bits
Pulls RSTSEL to GND. Sets the output value to
JP11 Closed
negative full-scale on resets
Pulls USB/BTC to GND. Sets the input format for
JP13 Closed
the DAC to straight binary
Sets the DAC8728 to unipolar operation by routing
JP14 2-3
the AV
SS
pin to AGND.
Sets the DV
DD
input to the DAC8728 to +3.3V from
JP15 1-2
pin-10 on the J4 header
Routes the OFFSET_B pin directly to AGND which
JP16 Closed
is required for single-supply operation
LDAC is controlled by the output of the U12 AND
JP17 1-2
gate.
U12 AND gate is only controlled by LDAC_CTRL
JP18 Open
from the 2Y3 output of the SN74LVC139
JP19 1-2 +3.3V is routed to JP20
The output for the JP19 jumper (3.3V default) is
JP20 1-2
routed to the IOV
DD
input of the DAC8728.
After confirming that jumpers are installed correctly on the EVM, power can be applied to the board.
Power must be applied in this order: IOV
DD
, then DV
DD
, then AV
DD
and AV
SS
. Even though the EVM
incorporates some basic power-supply filtering, a clean, well-regulated power supply is required to obtain
the performance results described in the
product data sheet .
Once the EVM is powered, the user can apply the appropriate parallel data and control signals to the EVM
using J1 and J6. The DAC8728EVM can also be connected directly to the 5-6k Interface Board for use
with a variety of C5000 and C6000 series DSP Starter Kits (DSKs), available from Texas Instruments. The
parallel control and data connectors are designed to allow pattern generators and/or logic analyzers to be
connected to the EVM using standard ribbon type cables on 0.1” centers.
13 SBAU161 – February 2010 DAC8728EVM
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