EVM Stacking
3-3
EVM Operation
3.3
EVM Stacking
The stacking of EVMs is possible if there is a need to evaluate two DAC8574s
to yield a total of eight channel outputs. A maximum of two EVMs are allowed
since the output terminal, J4, dictates the number of DAC channels that can
be connected without colliding. Table 3 - 2 shows how the DAC output
channels are mapped into the output terminal, J4, with respect to the jumper
position of W2, W11, W12 and W13.
Table 3 - 2. DAC Output Channel Mapping
Reference
Jumper Position
Function
1 - 2
DAC output A (V
OUT
A) is routed to J4 - 2.
W2
2 - 3
DAC output A (V
OUT
A) is routed to J4 - 10.
1 - 2
DAC output B (V
OUT
B) is routed to J4 - 4.
W11
2 - 3
DAC output B (V
OUT
B) is routed to J4 - 12.
1 - 2
DAC output C (V
OUT
C) is routed to J4 - 6.
W12
2 - 3
DAC output C (V
OUT
C) is routed to J4 - 14.
1 - 2
DAC output D (V
OUT
D) is routed to J4 - 8.
W13
2 - 3
DAC output D (V
OUT
D) is routed to J4 - 16.
In order to allow exclusive control of each EVM that are stacked together, each
DAC8574 EVM must have its own unique I
2
C address. This is accomplished
by configuring the address jumpers W7 through W10 (refer to the data sheet
for I
2
C addressing).
The LDAC signal can be shared to have a synchronous DAC output update
and is hardware driven by GPIO0. If controlling the LDAC through software is
desired, the GPIO0 signal must be set low through software or the J2 pin 2 can
be pin strapped to DGND.
3.4
The Output Op-Amp
The EVM includes an optional signal conditioning circuit for the DAC output
through an external operational amplifier, U2. Only one DAC output channel
can be monitored at any given time for evaluation since the odd numbered pins
(J4 - 1 to J4 - 15) are tied together. The output op-amp is set to a gain of 2
configuration by default. Nevertheless, the raw outputs of the DAC can be
probed through the even pins of J4, the output terminal, which also provides
mechanical stability when stacking or plugging into any interface card. In
addition, it provides easy access for monitoring up to eight DAC channels
when stacking two EVMs together, refer to Section 3.3 above.
The following sections describe the different configurations of the output
amplifier, U2.
Содержание DAC8574
Страница 1: ...DAC8574 Evaluation Module June 2003 Data Acquisition Digital Analog Converters User s Guide SLAU109 ...
Страница 17: ...PCB Layout 2 5 PCB Design and Performance Figure 2 7 Drill Drawing ...
Страница 19: ...EVM Performance 2 7 PCB Design and Performance Figure 2 9 INL and DNL Characterization Graph of DAC A ...
Страница 20: ...EVM Performance 2 8 Figure 2 10 INL and DNL Characterization Graph of DAC B ...
Страница 21: ...EVM Performance 2 9 PCB Design and Performance Figure 2 11 INL and DNL Characterization Graph of DAC C ...
Страница 22: ...EVM Performance 2 10 Figure 2 12 INL and DNL Characterization Graph of DAC D ...
Страница 24: ...2 12 ...