Introduction
4
SLAU773 – May 2018
Copyright © 2018, Texas Instruments Incorporated
DAC5652AEVM User's Guide
1.3
DAC5652AEVM Operation Procedure
The DAC5652AEVM can be set up in a variety of configurations to accommodate a specific mode of
operation. Before starting evaluation, the user must decide on the configuration and make the appropriate
connections or changes. The demonstration board comes with following factory-set configuration:
Single clock source mode using a clock input at J3. Single clock source driving CLK_1, WRT_1, CLK_2,
and WRT_2 from WRT_1 input.
•
Transformer-coupled outputs using transformer T1 and T2.
•
The converter is set to operate with internal reference.
•
Full-scale output current set to 19.2 mA through RBIAS resistor R22 and R23 (GSET jumper on J10
installed between pins 10 and 11 and JP2 and JP3 installed).
•
The DAC5652A output is enabled (sleep mode disabled). Sleep jumper on J10 is installed between
pins 4 and 5.
•
Data input set to dual port mode. Mode jumper on J10 is installed between pins 2 and 3.
•
Dual input power supplies required.
•
VFUSE function disabled. JP1 installed.
2
Power Requirements
The demonstration board requires only two power supplies. The first, +3.3 VA, is required to be +3.3 VDC
at banana jack J11 with the return going to J12. This supply is the analog supply for the DAC5652A. The
second, +3.3 VB, is required to be +3.3 VDC at banana jack J13 with the return to J14. This supply is the
d3.3-V supply for the DAC5652A.
2.1
External Reference Operation
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO
pin using test point 1. The use of an external reference may be considered for applications that require
higher accuracy and drift performance, or to add the ability of dynamic gain control. The reference input
has a high impedance and can easily be driven by various sources.
3
Schematic Diagram
The schematic diagram for the EVM can be down loaded from the product folder at
3.1
Input Clock
The DAC5652AEVM default operation setting is with a single-ended input clock sent to the DAC5652A. A
3 V
PP
, 1.5-V offset, 50% duty cycle external square wave is applied to SMA connector J3. This input
represents a 50-
Ω
load to the source. In order to preserve the specified performance of the DAC5652A
converter, the clock source features very low jitter. Using a clock with a 50% duty cycle gives optimum
dynamic performance. Options are provided to operate the two DACs with separate clocks. Another option
allows the user to provide separate write enables when using interleave mode. See
for proper
board configuration.
