User's Guide
SCAU027B – March 2009 – Revised March 2011
Low Phase Noise Clock Evaluation Module
Contents
1
Features
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2
General Description
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3
Signal Path and Control Circuitry
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4
Getting Started
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5
Input Clock Selection
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6
Operating Mode Selection
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7
Output Buffer Termination
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8
Schematic
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1
Features
•
Easy-to-use evaluation module to generate low
phase noise clocks
•
Easy device setup
•
Rapid configuration
•
Control pins configurable through jumpers
•
Requires 3.3-V power supply
•
Single-ended or crystal input clock reference
•
Termination available for LVPECL, LVDS, and
LVCMOS output clocks
Figure 1. CDCM6100xEVM Evaluation Board
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1
SCAU027B – March 2009 – Revised March 2011
Low Phase Noise Clock Evaluation Module
© 2009–2011, Texas Instruments Incorporated