CDCM6100x
XIN
CDCM6100x
R69
50
(Optional)
W
C61
100 nF
J101
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Operating Mode Selection
5.1
Configuring a Crystal Input
The EVM is available with an optional 25-MHz crystal. The EVM offers a dual footprint for a 6-pin (5 mm ×
7 mm) and 4-pin (3 mm x 5 mm) crystal. For a parallel load resonant crystal, the configuration should be
similar to that shown in
Note: This configuration assumes that the crystal is placed very closed to the XIN pin on the device.
Figure 2. CDCM6100xEVM Configuration with Parallel Load Resonant Crystal Clock Source
5.2
Configuring a Single-Ended Input
For a single-ended clock, remove the crystal if the board already has a crystal installed. Use SMA
connector J101 for a single-ended input clock. Place a 50-
Ω
resistor in R69 if the clock is provided from a
signal generator and if the signal generator requires a 50-
Ω
load for its operation. If the input clock is
provided from another board or the LVCMOS buffer, do not place any resistor here.
Capacitor C61 (100 nF) is required for ac coupling, as shown in
.
Figure 3. Single-Ended Connection Configuration
6
Operating Mode Selection
The CDCM6100x is a PLL-based device and offers several modes of operation. Selection of the available
control pins provides a set of output frequencies with different signaling levels. See the respective product
data sheets for detailed device configuration information.
6.1
Prescaler Divider and Feedback Divider Settings
JP17 (PR1) and JP18 (PR0) are the control pin jumpers for Prescalar Divider and Feedback Divider
selection, respectively. Use these jumpers only for logic '0'. These pins have internal 150-k
Ω
pull-up
resistors; it is recommended to use the internal pull-up resistor only for logic '1'.
summarizes the available prescaler divider and feedback divider values with the corresponding
PFD frequency range.
3
SCAU027B – March 2009 – Revised March 2011
Low Phase Noise Clock Evaluation Module
© 2009–2011, Texas Instruments Incorporated
